CBTL05024BSHP datasheet(3/21 Pages) NXP

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CBTL05024

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Product data sheet

Rev. 4 — 27 March 2014

3 of 21

NXP Semiconductors

CBTL05024

High performance MUX/deMUX switch for Thunderbolt applications

 When AUXIO_EN = 1, TB_ENA = 0 and DP_PD = 1, the CBTL05024 is in

Detect mode

 AUXIO+ and AUXIO

 of the TB MUX are disabled

 LS path is selected in DP MUX

 CA_DET and HPD buffers are on

 When the CBTL05024 is in Detect mode, this chip consumes < 18

W

 Patent-pending high bandwidth analog pass-gate technology

 Very low intra-pair differential skew (5 ps typical)

 Back current protection on connector pins (AUXIO+/

, DPMLO+/, CA_DET and HPD

pins)

 All channels support rail-to-rail input voltage

 All CMOS input buffer with hysteresis

 Single 3.3 V

 10 % power supply

 HVQFN24 3 mm

 3 mm package, 0.4 mm pitch, exposed center pad for thermal relief

and electrical ground

 ESD: 2000 V HBM, 1000 V CDM

 Operating temperature range

20 C to 85 C

Ordering information

[1]

Maximum package height is 1 mm.

3.1 Ordering options

Table 1.

Ordering information

Type number

Topside

marking

Package

Name

Description

Version

CBTL05024BS

024

HVQFN24

plastic thermal enhanced very thin quad flat package; no leads;

24 terminals; body 3

 3  0.85 mm[1]

SOT905-1

Table 2.

Ordering options

Type number

Orderable

part number

Package

Packing method

Minimum

order quantity

Temperature

CBTL05024BS

CBTL05024BSHP

HVQFN24

Reel 13” Q2/T3

*standard mark SMD

6000

Tamb = 20 Cto+85 C

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