CBTL05024

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© NXP Semiconductors N.V. 2014. All rights reserved.

Product data sheet

Rev. 4 — 27 March 2014

12 of 21

NXP Semiconductors

CBTL05024

High performance MUX/deMUX switch for Thunderbolt applications

9.4 Control signals characteristics

[1]

The leakage current on CA_DET pin must not drive the 1 M

 pull-down to a HIGH level.

input voltage

LSTX/LSRX to DPMLO+/DPMLO



channel

0.3

-

V

common-mode input voltage

DP+/DP

 and DPMLO+/DPMLO

0-

V

differential input voltage

DP+/DP

 to DPMLO+/DPMLO

channel

--

1.4

V

HIGH-level input leakage

current

DP+/DP

 and DPMLO+ pins;

--

1

A

DPMLO

 pins; V

--

5

A

LOW-level input leakage

current

DP+/DP

 and DPMLO+/DPMLO pins;

--

1

A

Table 14.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Table 15.

CA_DET input buffer characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-level input voltage

2

-

-

V

LOW-level input voltage

-

-

0.8

V

input leakage current

[1] --

0.1

A

Table 16.

HPD input buffer characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-level input voltage

2

-

5

V

LOW-level input voltage

-

-

0.8

V

Table 17.

TB_ENA, DP_PD or AUXIO_EN input characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

HIGH-level input voltage

CMOS inputs

0.7

 V

DD

--

V

LOW-level input voltage

CMOS inputs

-

-

0.3

 V

DD

V

input leakage current

-1

10

A

Table 18.

CA_DETOUT and HPDOUT output buffer characteristics

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

LOW-level output voltage

0

-

0.4

V

HIGH-level output voltage

2.5

-

-

V

propagation delay

-

50

100

ns