AM6412...ALV datasheet(116/244 Pages) TI

116 / 244 page

7.10.2.2.2 Power-Down Sequencing

Figure 7-6 describes the device power-down sequencing.

AM64x_ELCH_02

MCU_PORz

MCU_OSC0_XI, MCU_OSC0_XO

VSYS

VMON_VSYS

VSYS, VMON_VSYS

VPP

VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,

(1)

VDDSHV4 , VDDSHV5 , VDDA_3P3_SDIO, VDDA_3P3_USB0,

(1)

VMON_3P3_SOC, VMON_3P3_MCU

VDDS_OSC, VDDSHV_MCU , VDDSHV0 , VDDSHV1 , VDDSHV2 , VDDSHV3 ,

(2)

VDDSHV4 , VDDSHV5 , VDDA_MCU, VDDA_ADC0, VDDA_PLL0, VDDA_PLL1,

(2)

VDDA_PLL2, VDDA_1P8_SERDES0, VDDA_1P8_USB0, VMON_1P8_MCU,

VMON_1P8_SOC, VDDA_TEMP0, VDDA_TEMP1, VDDS_MMC0

VDDS_DDR, VDDS_DDR_C

VDD_CORE

(3)(5)

VDD_CORE

, VDDR_CORE , VDDA_0P85_SERDES0_C,

(5)

(4)(5)

VDDA_0P85_SERDES0, VDDA_0P85_USB0,

VDD_DLL_MMC0, VDD_MMC0

Hi-Z

Figure 7-6. Power-Down Sequencing

1. VDDSHV_MCU and VDDSHVx [x=0-5] when operating at 3.3V.

2. VDDSHV_MCU and VDDSHVx [x=0-5] when operating at 1.8V.

3. VDD_CORE when operating at 0.75V.

4. VDD_CORE when operating at 0.85V.

5. The potential applied to VDDR_CORE must never be greater than the potential applied to VDD_CORE +

0.18V during power-up or power-down. This requires VDD_CORE to ramp up before and ramp down after

VDDR_CORE when VDD_CORE is operating at 0.75V. VDD_CORE does not have any ramp requirements

beyond the one defined for VDDR_CORE. VDD_CORE and VDDR_CORE are expected to be powered by

the same source so they ramp together when VDD_CORE is operating at 0.85V.

AM6442, AM6441, AM6421, AM6412, AM6411

SPRSP56D – JANUARY 2021 – REVISED JULY 2022

www.ti.com

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