MPFS025T datasheet(25/50 Pages) MICROCHIP

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Programmable Logic Subsystem

The following section describes the programmable logic subsystem.

4.1

Clock Management

In each PolarFire SoC FPGA, there are eight DLLs and eight PLLs to provide flexible clock generation and

management capabilities. In addition to these DLLs and PLLs, up to 15 transceiver lane transmit PLLs are also

available.

The following are key highlights of the clock management architecture.

• High-speed buffers and routing for low-skew clock distribution

• Frequency synthesis and phase shifting

• Low-jitter clock generation and jitter filtering

4.1.1

DLL

The DLL provides a calculated PVT compensated delay to the I/O’s digital delay lines and delay or phase-shifted

clocks to the FPGA fabric.

The following are the major modes to which the DLL can be configured.

• Time reference mode—the DLL takes a single clock as an input and determines how many delay line buffer taps

are required for a signal to pass through them to rotate a signal. The main use of time reference mode is to

know how many delay taps are needed to delay the clock by 90 degrees. The value is then provided to the data

strobe signal (DQS)/DQSn input signals for double data rate (DDR) memory controllers to delay all DQS/DQSn

signals by the required 90-degree phase shift to capture the data from the memory devices. Multiple memory

interfaces of the same clock rate can reuse the same DLL with lane level controls for PVT updates.

• Clock injection delay mode—the DLL can be used to compensate for the clock injection delay associated with

the source synchronous receive interfaces. The DLL can match delays for the global, regional, and high-speed

bank clocks. There are two outputs from the DLL in this mode: a x1 output fixed in time and another output that

can be divided by x1, x2, or x4 and can be phase shifted.

4.1.2

PLL

The programmable delta-sigma, low-jitter fractional PLLs are multi-function and general-purpose frequency

synthesizers, as shown in the PLL Block Diagram. Wide input and output ranges along with the best-in-class jitter

performance allow these PLLs to be used for almost any clocking application. With excellent supply noise immunity,

the PLL is ideal for use in noisy FPGA environments.

• The PLL output clock is available in eight phases with 45-degree phase differences. All eight phases are

selectable to drive four separate outputs from the PLL, where each output can select any of the eight phases

independent of other output selections and each output can also be driven to a zero output when not used.

• Each of the four outputs from the PLL can then be divided independently for any value from 1 to 127. Each of

the PLL outputs can have the output divider released by up to seven VCO/4 cycles. The delayed outputs can be

set independently for each output clock.

• Fractional-N (24-bit accuracy) capability is added to the feedback divider to have the VCO frequency be a

non-integer divide of the reference clock input frequency. The base frequency is applied to all PLL outputs.

• The PLL supports glitch-free start and stop on any one of the four outputs independently by either a register

map or a fabric control. This capability also allows the output divider values and the VCO/4 phase selection to

be modified glitch-free during the time that the clock is stopped.

• For fine granularity phase control of the PLLs, they can be cascaded with DLLs located near the PLLs, whereby

the DLL delay lines can be used in a process, voltage, and temperature (PVT) compensated or non-PVT

compensated mode to provide the phase control needed.

The following illustration shows the flow of the PLL functionality.

Programmable Logic Subsystem

and its subsidiaries

Overview

DS60001656C-page 25

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