Figure 4-1. PLL Block Diagram

FPGA Feedback Clock

Reference Clock0

FOUT0

FOUT1

FOUT2

FOUT3

FOUT[0:3]

Phase Select

Charge

Pump

LOCK

Internal Feedback

Path

Reference Clock1

Lock

Detect

PFD

÷

1-63

÷

1-4095

÷

1-127

÷

1-127

÷

1-127

÷

1-127

VCO

FPGA Feedback Clock

Reference Clock0

FOUT0

FOUT1

FOUT2

FOUT3

FOUT[0:3]

Phase Select

Charge

Pump

LOCK

Internal Feedback

Path

Reference Clock1

Lock

Detect

PFD

÷

1-63

÷

1-4095

÷

1-127

÷

1-127

÷

1-127

÷

1-127

VCO

4.1.3

Clock Network

The clock network is designed to route clocks and asynchronous reset signals to large sections of the fabric with

limited skew. On occasion, the network can also be used for other high fanout signals that can tolerate long delays,

such as non-timing-critical synchronous enables or resets. There are two main clock networks for the FPGA fabric,

global, and regional clocks.

4.1.3.1

Global Clocks

There are 24 clocks on the device with global, low-skew scope to all synchronous elements. The global can be

divided into left and right sides of the device. Thus, the number of global clocks can increase to 48 total clocks with

24 in the left and 24 in the right.

4.1.3.2

Regional Clocks

There are up to 38 regional clock domains that interface to the edges of the device. The regional clocks provide a

fixed number of logic elements based on the size of the device. Up to 14 clocks are available for the FPGA I/Os and

up to 24 clocks are available for the transceiver lanes, one for each lane direction. These are the fast insertion clock

networks used to move data in and out of the fabric.

4.2

Debug Probe System

Two specified user I/Os can be configured (at design capture stage) as either two, single-ended live probes or

one, differential live probe. These live probes can provide read access to any register in the FPGA fabric, to the

output pipeline registers in the LSRAMs, and to all the registers in the math block in real time without having to

re-instrument the code. A snapshot of all internal probe points can be created and read-out asynchronously. The

live-probe feature can be considered a two-channel oscilloscope, whose two channels can be routed out to I/Os for

external observation and to internal ports for fabric design observation. Selecting different probe points within the

PolarFire SoC FPGA occurs dynamically through commands over the JTAG port using SmartDebug. Reprogramming

of the FPGA is not required.

The features of the debug probe system are:

• Active probe allows dynamic asynchronous read and write to a flip-flop or a probe point. This enables quick

internal observation of the logic output or experimentation on how the logic will be affected by writing to a probe

point.

• Memory debug allows dynamic asynchronous read and write to a µSRAM or a large SRAM block to quickly

verify if the content of the memory is changing as expected.

• Probe insertion allows routing of nodes or debug points in the FPGA design externally through unused I/Os. An

oscilloscope/logic analyzer can be attached to monitor them as live signals.

4.3

I/Os

PolarFire SoC FPGA device user I/Os support multiple I/O standards while providing the high bandwidth needed to

maximize the internal logic capabilities of the device and achieve the required system-level performance.

Programmable Logic Subsystem

© 2021 Microchip Technology Inc.

and its subsidiaries

Overview

DS60001656C-page 26