MPFS025T datasheet(27/50 Pages) MICROCHIP

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4.3.1

Low-Power, High-Speed Transceiver Lane

All PolarFire SoC FPGAs contain state-of-the-art low-power transceiver lane capabilities from speeds as low as 250

Mbps up to 12.7 Gbps. The PMA is designed to support multiple protocols (as listed in the following table) with

state-of-the-art control and debug features. PCI Express Gen1 or Gen2 support is provided by a hard macro. All other

protocols are implemented with a soft IP. Serial Gigabit Ethernet is also supported with GPIO 3.3 V LVDS differential

pairs. A single transmit PLL can provide a high-speed clock up to four transceiver lanes.

Table 4-1. Transceiver Lane Protocol Support

Protocol

Data Rate (Gbps)

Channels Bonded

PCIe

2.5, 5

1, 2, 4

Interlaken

6.375, 12.7

1–16

10GBASE-KR

10.3125–12.7

SGMII/QSGMII

1.25–5

XAUI

3.125

RXAUI

3.125, 6.25

2, 3, 4, 6

HiGig/HiGig+/HiGiGII

3.75–4.065

Fiber Channel

0.6144–12.165

SRIO

1.25–6.3

1, 2, 4, 8

SATA

1.5–6

JESD204B

0.5–12.5

1–4

Display Port

2, 5, 8

SDI

0.277–11.88

4.3.1.1

Low-Power Transceiver Lane Features

The following are features of the low-power transceiver lane.

• Advanced low-power modes

• Programmable transmit amplitude and emphasis control

• Low-speed CDR operation with support for 270 Mbps SMPTE serial line rates

• Continuous time linear equalization (CTLE) and decision feedback equalization (DFE) for long-reach or

backplane applications

• Auto-adaption at receiver equalization and integrated eye monitor feature for easy serial link tuning

• Eye monitor and/or equalization can be powered down to reduce power if not needed

• Out-of-band, electrical idle signaling capability for SAS, SATA, and PCIe

• Multiple loopback modes for test and debug

• Transmit jitter attenuation for loop timing applications (SyncE compatible)

• Hot-socketing capable

• IEEE 1149.6 AC JTAG

• Adjacent channel loopback modes allow transceiver lane data streams to remain active during FPGA fabric

programming

4.3.1.2

Transmitter

The transmitter is fundamentally a parallel-to-serial converter with a conversion ratio of 8, 10, 16, 20, 32, 40, 64,

or 80 bits. It allows the designer to trade-off data path width for timing margin in high-performance designs. These

transmitter outputs drive the PC board with a differential output signal. TX_CLK is the appropriately divided serial

Programmable Logic Subsystem

and its subsidiaries

Overview

DS60001656C-page 27

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