MPFS025T datasheet(17/50 Pages) MICROCHIP

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that it is a cacheable region allowing for data stored to the scratchpad to also be cached in a master’s L1 data cache

resulting in faster access.

3.4.1.1

DDR Memory Controller

The hardened, 32-bit DDR memory controller supports the following features:

• DDR4, LPDDR4, DDR3, and LPDDR3 memory support

• Dual Rank support for dual die packages

• Max rate support 1600 Mbps

• DDR memory test feature

• Reorder queue to optimize DDR performance

• Two AXI interfaces

– 128-bit from CPU L2 Cache

– 64-bit from central AXI switch

• 32 outstanding transactions per AXI interface

• An integrated Clock Domain Crossing (CDC) circuit allowing the DDR controller clock to be independent of the

CPU clock

• A dedicated PLL for DDR clock generation

It can support up to 8 GB of external DDR4 memory and 4 GB of DDR3 memory. SECDED capability is also provided

when configured to a 36-bit bus width, as listed in the following table.

Table 3-3. DDR Memory Controller

Configuration

Active Pads

Lane 0

Lane 1

Lane 2

Lane 3

Lane 41

5x8 DDR with SECDED

DDRx8

DDRx8 (4 used)

4x8 DDR

DDRx8

Not used

3x16 DDR with SECDED

DDRx16

DDRx16 (4 used)

2x16 DDR

DDRx16

Not used

3x16 DDR with SECDED

DDRx8

—

DDRx8 (2 used)

2x16 DDR

DDRx8

—

1x16 DDR with SECDED

DDRx16

—

DDRx16 (2 used)

1x16 DDR

DDRx16

—

1x32 DDR

DDRx32

—

Note:

Lane 4 is only 4 bits wide, the upper data bits on the DDR memory are not connected.

3.4.1.2

Processor Interconnect

There are two interconnect switches built into the MSS. First, there is a fully populated coherent switch that

manages coherence through the memory subsystems and provides a deterministic data path to the L2 memory

subsystem when it is configured as a loosely integrated memory. Additionally, a central AMBA I/O switch manages

the interconnect between the CPU complex, the peripheral I/O space, the hardened DDR memory controller, and the

FPGA fabric. The AMBA switch also includes Quality of Service (QoS) features. The QoS feature is essentially a

4-bit value denoting priority for the data path. The central I/O switch is partially connected and supports 15 masters

with nine slaves. The AMBA switch also contains a Memory Protection Unit (MPU) scheme that mimics the Physical

Memory Protection (PMP) scheme defined in the RISC-V Privileged Specification. Specifically, the bus masters listed

in the following table pass through the AMBA MPU. PMP region address granularity start at 4096 and increase by

powers of two. Regions can be defined to support execution, read or write. An additional lock bit can be set on each

Microprocessor Subsystem

and its subsidiaries

Overview

DS60001656C-page 17

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