PolarFire SoC uses UltraSoC debug infrastructure to compress and transport debug information over a variety of

ports.

• Ethernet

• JTAG

• FPGA fabric

3.2.3

AXI Bus Monitors

There are two AXI bus monitors within the MSS that allow, at run time, observation of AXI transactions. They can

be used for debugging, reporting diagnostics, performance profiling, bare metal security, and other applications. For

example, the AXI monitors can passively filter on specific addresses, which master is performing the R/W, without

affecting traffic at run time.

The AXI-64 bus monitor is configured to provide full address and data trace on the slave side of the AXI switch.

The AXI-128 bus monitor is configured to provide full address trace on the AXI4-128 bus connecting the MSS

L2 interface to the DDR memory. Data trace is not supported in this case. This allows the ability to trace the

effectiveness of the cache and DDR response rates

3.2.4

Fabric Monitor

PolarFire SoC incorporates a FPGA Fabric Monitor within the MSS. 32 General purpose inputs to the MSS from the

FPGA are available for monitoring FPGA logic. Eight general purpose outputs can be driven into the FPGA fabric to

control either users logic or debug instrumentation. The Fabric Monitor pipes data over the debug transport layer and

out through one of the defined debug ports, most commonly Ethernet.

3.2.5

SmartDebug

Two specified user I/Os is configured (at design capture stage) as either two single-ended live probes or one

differential live probe. These live probes provide read access to any register in the FPGA fabric to the output pipeline

registers in the LSRAMs and to all the registers in the math block in real-time without having to re-instrument the

code. A snapshot of all internal probe points is created and read out asynchronously. The live-probe feature is like

a two-channel oscilloscope, whose two channels can be routed out to I/Os for external observation, and to internal

ports to allow fabric design observation. Selecting different probe points within the device occurs dynamically through

commands over the JTAG port using SmartDebug. Reprogramming of the device is not needed.

The following are included in the debug probe system.

• Active probe allows dynamic asynchronous read and write to a flip-flop or a probe point. This enables quick

internal observation of the logic output or experimentation on how the logic is affected by writing to a probe

point.

• Memory debug allows dynamic asynchronous read and write to a μSRAM or a large SRAM block to quickly

verify if the content of the memory is changing as expected.

• Probe insertion allows routing of nodes or debug points in the FPGA design externally through unused I/Os. An

oscilloscope/logic analyzer can be attached to monitor them as live signals.

3.3

Interrupts

Each hardware thread (hart) in PolarFire SoC has support for the following interrupts: local (including software

and timer) and global. Local interrupts are signaled directly to an individual hart with a dedicated interrupt value.

This allows for reduced interrupt latency as there is no arbitration required to determine which hart will service a

given request, nor additional memory accesses required to determine the cause of the interrupt. Software and timer

interrupts are local interrupts generated by the Core Local Interruptor (CLINT). Global interrupts by contrast, are

routed through a Platform-Level Interrupt Controller (PLIC), which can direct interrupts to any hart in the system via

the external interrupt. Decoupling global interrupts from the hart(s) allows the design of the PLIC to be tailored to

the platform, permitting a broad range of attributes like the number of interrupts and the prioritization and routing

schemes. By default all interrupts are handled in machine mode. The U54s, which support supervisor mode, can

selectively delegate interrupts to supervisor mode.

Microprocessor Subsystem

© 2021 Microchip Technology Inc.

and its subsidiaries

Overview

DS60001656C-page 15