show this measurement. During the internally self-timed write cycle, any attempts to read from or write to

the memory array will not be processed.

Figure 7-4. Write Cycle Timing

t

WR

Stop

Condition

Start

Condition

Data Word n

ACK

D0

SDA

Stop

Condition

SCL

8

9

ACK

First Acknowledge from the device

to a valid device address sequence after

write cycle is initiated. The minimum t

WR

can only be determined through

the use of an ACK Polling routine.

9

7.5

Write Protection

The AT24C01C/AT24C02C utilizes a hardware data protection scheme that allows the user to

will be set if the WP pin is at GND or left floating.

Table 7-1. AT24C01C/AT24C02C Write-Protect Behavior

WP Pin Voltage

Part of the Array Protected

Full Array

GND

None － Write Protection Not Enabled

The status of the WP pin is sampled at the Stop condition for every byte write or page write operation

prior to the start of an internally self‑timed write cycle. Changing the WP pin state after the Stop condition

has been sent will not alter or interrupt the execution of the write cycle.

If an attempt is made to write to the device while the WP pin has been asserted, the device will

acknowledge the device address, word address and data bytes, but no write cycle will occur when the

Stop condition is issued. The device will immediately be ready to accept a new read or write command.

AT24C01C/AT24C02C

Write Operations

Datasheet

DS20006111A-page 20