The master can use the Stop condition to end a data transfer sequence with the AT24C01C/AT24C02C,

which will subsequently return to Standby mode. The master can also utilize a repeated Start condition

instead of a Stop condition to end the current data transfer if the master will perform another operation.

Refer to Figure 5-1 for more details.

5.3

Acknowledge and No-Acknowledge

After every byte of data is received, the receiving device must confirm to the transmitting device that it

has successfully received the data byte by responding with what is known as an Acknowledge (ACK).

An ACK is accomplished by the transmitting device first releasing the SDA line at the falling edge of the

eighth clock cycle followed by the receiving device responding with a logic ‘0’ during the entire high period

of the ninth clock cycle.

When the AT24C01C/AT24C02C is transmitting data to the master, the master can indicate that it is done

receiving data and wants to end the operation by sending a logic ‘1’ response to the AT24C01C/

AT24C02C instead of an ACK response during the ninth clock cycle. This is known as a No-Acknowledge

(NACK) and is accomplished by the master sending a logic ‘1’ during the ninth clock cycle, at which point

the AT24C01C/AT24C02C will release the SDA line so the master can then generate a Stop condition.

The transmitting device, which can be the bus master or the Serial EEPROM, must release the SDA line

at the falling edge of the eighth clock cycle to allow the receiving device to drive the SDA line to a logic ‘0’

to ACK the previous 8-bit word. The receiving device must release the SDA line at the end of the ninth

clock cycle to allow the transmitter to continue sending new data. A timing diagram has been provided in

Figure 5-1 to better illustrate these requirements.

Figure 5-1. Start Condition, Data Transitions, Stop Condition and Acknowledge

SCL

SDA

SDA

Must Be

Stable

SDA

Change

Allowed

SDA

Change

Allowed

Acknowledge

Valid

Stop

Condition

Start

Condition

1

2

8

9

SDA

Must Be

Stable

Acknowledge Window

The transmitting device (Master or Slave)

must release the SDA line at this point to allow

the receiving device (Master or Slave) to drive the

SDA line low to ACK the previous 8-bit word.

The receiver (Master or Slave)

must release the SDA line at

this point to allow the transmitter

to continue sending new data.

5.4

Standby Mode

The AT24C01C/AT24C02C features a low-power Standby mode that is enabled when any one of the

following occurs:

•

A valid power-up sequence is performed (see Power-Up Requirements and Reset Behavior).

•

A Stop condition is received by the device unless it initiates an internal write cycle (see Write

Operations).

•

At the completion of an internal write cycle (see Write Operations).

AT24C01C/AT24C02C

Device Operation and Communication

Datasheet

DS20006111A-page 14