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AT24C01C 数据表(PDF) 22 Page - Microchip Technology

部件名 AT24C01C
功能描述  I²C-Compatible (Two-Wire) Serial EEPROM 1‑Kbit (128 x 8), 2‑Kbit (256 x 8)
PDF  45 Pages
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制造商  MICROCHIP [Microchip Technology]
网页  http://www.microchip.com
标志 MICROCHIP - Microchip Technology

AT24C01C 数据表(HTML) 22 Page - Microchip Technology

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Figure 8-2. Random Read
SCL
SDA
Start
by
Master
Device Address Byte
Word Address Byte
MSB
MSB
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
0
1
0
A
2
A
1
A
0
0
0
Dummy Write
Start
by
Master
Device Address Byte
Data Word (n)
Stop
by
Master
MSB
MSB
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
0
1
0
A
2
A
1
A
0
1
0
D7 D6
D5 D4 D3
D2 D1
D0
1
A7
A6
A5
A4
A3
A2
A1
A0
0
ACK
from
Slave
ACK
from
Slave
ACK
from
Slave
NACK
from
Master
8.3
Sequential Read
Sequential reads are initiated by either a current address read or a random read. After the bus master
receives a data word, it responds with an Acknowledge. As long as the EEPROM receives an ACK, it will
continue to increment the word address and serially clock out sequential data words. When the maximum
memory address is reached, the data word address will roll-over and the sequential read will continue
from the beginning of the memory array. All types of read operations will be terminated if the bus master
does not respond with an ACK (it NACKs) during the ninth clock cycle. After the NACK response, the
master may send a Stop condition to complete the protocol, or it can send a Start condition to begin the
next sequence.
Figure 8-3. Sequential Read
SCL
SDA
Start
by
Master
ACK
from
Slave
ACK
from
Master
Device Address Byte
Data Word (n)
MSB
MSB
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
0
1
0
A
2
A
1
A
0
1
0
D7 D6
D5 D4 D3
D2 D1
D0
0
ACK
from
Master
NACK
from
Master
Stop
by
Master
ACK
from
Master
Data Word (n+1)
Data Word (n+2)
Data Word (n+x)
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
1
2
3
4
5
6
7
8
9
D7 D6
D5
D4 D3 D2
D1 D0
0
D7
D6 D5
D4 D3
D2 D1
D0
0
D7 D6 D5
D4 D3
D2 D1
D0
1
MSB
MSB
MSB
AT24C01C/AT24C02C
Read Operations
© 2018 Microchip Technology Inc.
Datasheet
DS20006111A-page 22



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