5.

Device Operation and Communication

digital serial interface to communicate with a host controller, commonly referred to as the bus master. The

master initiates and controls all read and write operations to the slave devices on the serial bus, and both

the master and the slave devices can transmit and receive data on the bus.

The serial interface is comprised of just two signal lines: Serial Clock (SCL) and Serial Data (SDA).

The SCL pin is used to receive the clock signal from the master, while the bidirectional SDA pin is used to

receive command and data information from the master as well as to send data back to the master.

Data is always latched into the AT24C01C/AT24C02C on the rising edge of SCL and always output from

the device on the falling edge of SCL. Both the SCL and SDA pin incorporate integrated spike

suppression filters and Schmitt Triggers to minimize the effects of input spikes and bus noise.

All command and data information is transferred with the Most Significant bit (MSb) first. During bus

communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data have

been transferred, the receiving device must respond with either an Acknowledge (ACK) or a

No-Acknowledge (NACK) response bit during a ninth clock cycle (ACK/NACK clock cycle) generated by

the master. Therefore, nine clock cycles are required for every one byte of data transferred. There are no

unused clock cycles during any read or write operation, so there must not be any interruptions or breaks

in the data stream during each data byte transfer and ACK or NACK clock cycle.

During data transfers, data on the SDA pin must only change while SCL is low, and the data must remain

stable while SCL is high. If data on the SDA pin changes while SCL is high, then either a Start or a Stop

condition will occur. Start and Stop conditions are used to initiate and end all serial bus communication

between the master and the slave devices. The number of data bytes transferred between a Start and a

Stop condition is not limited and is determined by the master. In order for the serial bus to be idle, both

the SCL and SDA pins must be in the logic-high state at the same time.

5.1

Clock and Data Transition Requirements

The SDA pin is an open-drain terminal and therefore must be pulled high with an external pull‑up resistor.

SCL is an input pin that can either be driven high or pulled high using an external pull‑up resistor. Data on

the SDA pin may change only during SCL low time periods. Data changes during SCL high periods will

indicate a Start or Stop condition as defined below. The relationship of the AC timing parameters with

respect to SCL and SDA for the AT24C01C/AT24C02C are shown in the timing waveform in Figure 4-1.

The AC timing characteristics and specifications are outlined in AC Characteristics.

5.2

Start and Stop Conditions

5.2.1

Start Condition

A Start condition occurs when there is a high-to-low transition on the SDA pin while the SCL pin is at a

stable logic ‘1’ state and will bring the device out of Standby mode. The master uses a Start condition to

initiate any data transfer sequence; therefore, every command must begin with a Start condition.

The device will continuously monitor the SDA and SCL pins for a Start condition but will not respond

unless one is detected. Refer to Figure 5-1 for more details.

5.2.2

Stop Condition

A Stop condition occurs when there is a low-to-high transition on the SDA pin while the SCL pin is stable

in the logic ‘1’ state.

AT24C01C/AT24C02C

Device Operation and Communication

Datasheet

DS20006111A-page 13