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CC2430-RTR1-F64 数据表(PDF) 92 Page - Texas Instruments |
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CC2430-RTR1-F64 数据表(HTML) 92 Page - Texas Instruments |
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92 / 234 page  CC2430 CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A Page 92 of 232 DMA Trigger number DMA Trigger name Functional unit Description 0 NONE DMA No trigger, setting DMAREQ.DMAREQx bit starts transfer 1 PREV DMA DMA channel is triggered by completion of previous channel 2 T1_CH0 Timer 1 Timer 1, compare, channel 0 3 T1_CH1 Timer 1 Timer 1, compare, channel 1 4 T1_CH2 Timer 1 Timer 1, compare, channel 2 5 T2_COMP Timer 2 Timer 2, compare 6 T2_OVFL Timer 2 Timer 2, overflow 7 T3_CH0 Timer 3 Timer 3, compare, channel 0 8 T3_CH1 Timer 3 Timer 3, compare, channel 1 9 T4_CH0 Timer 4 Timer 4, compare, channel 0 10 T4_CH1 Timer 4 Timer 4, compare, channel 1 11 ST Sleep Timer Sleep Timer compare 12 IOC_0 IO Controller Port 0 I/O pin input transition 13 IOC_1 IO Controller Port 1 I/O pin input transition 14 URX0 USART0 USART0 RX complete 15 UTX0 USART0 USART0 TX complete 16 URX1 USART1 USART1 RX complete 17 UTX1 USART1 USART1 TX complete 18 FLASH Flash controller Flash data write complete 19 RADIO Radio RF packet byte received/transmit 20 ADC_CHALL ADC ADC end of a conversion in a sequence, sample ready 21 ADC_CH11 ADC ADC end of conversion channel 0 in sequence, sample ready 22 ADC_CH21 ADC ADC end of conversion channel 1 in sequence, sample ready 23 ADC_CH32 ADC ADC end of conversion channel 2 in sequence, sample ready 24 ADC_CH42 ADC ADC end of conversion channel 3 in sequence, sample ready 25 ADC_CH53 ADC ADC end of conversion channel 4 in sequence, sample ready 26 ADC_CH63 ADC ADC end of conversion channel 5 in sequence, sample ready 27 ADC_CH74 ADC ADC end of conversion channel 6 in sequence, sample ready 28 ADC_CH84 ADC ADC end of conversion channel 7 in sequence, sample ready 29 ENC_DW AES AES encryption processor requests download input data 30 ENC_UP AES AES encryption processor requests upload output data Table 37: DMA Trigger Sources |
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