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CC2430-RTR1-F64 数据表(PDF) 96 Page - Texas Instruments |
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CC2430-RTR1-F64 数据表(HTML) 96 Page - Texas Instruments |
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96 / 234 page  CC2430 CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A Page 96 of 232 DMAREQ (0xD7) – DMA Channel Start Request and Status Bit Name Reset R/W Description 7:5 - 000 R0 Not used 4 DMAREQ4 0 R/W1 H0 DMA transfer request, channel 4 When set to 1 activate the DMA channel (has the same effect as a single trigger event.). Only by setting the armed bit to 0 in the DMAARM register, can the channel be stopped if already started. This bit is cleared when the DMA channel is granted access. 3 DMAREQ3 0 R/W1 H0 DMA transfer request, channel 3 When set to 1 activate the DMA channel (has the same effect as a single trigger event.). Only by setting the armed bit to 0 in the DMAARM register, can the channel be stopped if already started. This bit is cleared when the DMA channel is granted access. 2 DMAREQ2 0 R/W1 H0 DMA transfer request, channel 2 When set to 1 activate the DMA channel (has the same effect as a single trigger event.). Only by setting the armed bit to 0 in the DMAARM register, can the channel be stopped if already started. This bit is cleared when the DMA channel is granted access. 1 DMAREQ1 0 R/W1 H0 DMA transfer request, channel 1 When set to 1 activate the DMA channel (has the same effect as a single trigger event.). Only by setting the armed bit to 0 in the DMAARM register, can the channel be stopped if already started. This bit is cleared when the DMA channel is granted access. 0 DMAREQ0 0 R/W1 H0 DMA transfer request, channel 0 When set to 1 activate the DMA channel (has the same effect as a single trigger event.). Only by setting the armed bit to 0 in the DMAARM register, can the channel be stopped if already started. This bit is cleared when the DMA channel is granted access. DMA0CFGH (0xD5) – DMA Channel 0 Configuration Address High Byte Bit Name Reset R/W Description 7:0 DMA0CFG[15:8] 0x00 R/W The DMA channel 0 configuration address, high order DMA0CFGL (0xD4) – DMA Channel 0 Configuration Address Low Byte Bit Name Reset R/W Description |
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