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CC2430-RTR1-F64 数据表(PDF) 95 Page - Texas Instruments |
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CC2430-RTR1-F64 数据表(HTML) 95 Page - Texas Instruments |
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95 / 234 page  CC2430 CC2430 PRELIMINARY Data Sheet (rev. 1.03) SWRS036A Page 95 of 232 13.2.7 DMA registers This section describes the SFR registers associated with the DMA Controller DMAARM (0xD6) – DMA Channel Arm Bit Name Reset R/W Description 7 ABORT 0 R0/W DMA abort. This bit is used to stop ongoing DMA transfers. Writing a 1 to this bit will abort all channels which are selected by setting the corresponding DMAARM bit to 1 0 : Normal operation 1 : Abort channels all selected channels 6:5 - 00 R/W Not used 4 DMAARM4 0 R/W DMA arm channel 4 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion. 3 DMAARM3 0 R/W DMA arm channel 3 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion. 2 DMAARM2 0 R/W DMA arm channel 2 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion. 1 DMAARM1 0 R/W DMA arm channel 1 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion. 0 DMAARM0 0 R/W DMA arm channel 0 This bit must be set in order for any DMA transfers to occur on the channel. For non-repetitive transfer modes, the bit is automatically cleared upon completion. |
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