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VL53L4CD 数据表(PDF) 13 Page - STMicroelectronics |
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VL53L4CD 数据表(HTML) 13 Page - STMicroelectronics |
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13 / 37 page ![]() Figure 14. Data format (sequential read) S As ADDRESS[7:0] Am DATA[7:0] P 0x53 (read) Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] Am DATA[7:0] S As ADDRESS[7:0] INDEX[7:0] As P 0x52 (write) INDEX[15:8] As 3.1 I²C interface - timing characteristics Timing characteristics are shown in the following tables. Refer to Figure 15. I²C timing characteristics for an explanation of the parameters used. Timings are given for all PVT conditions. Table 5. I²C interface - timing characteristics for fast mode plus (1 MHz) Symbol Parameter Minimum Typical Maximum Unit FI2C Operating frequency 0 - 1000 kHz tLOW Clock pulse width low 0.5 - - μs tHIGH Clock pulse width high 0.26 - - tSP Pulse width of spikes that are suppressed by the input filter - - 50 ns tBUF Bus free time between transmissions 0.5 - - μs tHD.STA Start hold time 0.26 - - tSU.STA Start setup time 0.26 - - tHD.DAT Data in hold time 0 - 0.9 tSU.DAT Data in setup time 50 - - ns tR SCL/SDA rise time - - - - 120 tF SCL/SDA fall time - - 120 tSU.STO Stop set-up time 0.26 - - μs Ci/o Input/output capacitance (SDA) - - 10 pF Cin Input capacitance (SCL) - - 4 CL Load capacitance - 140 550 VL53L4CD I²C interface - timing characteristics DS13812 - Rev 5 page 13/37 |
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