HVLED007 datasheet(19/33 Pages) STMICROELECTRONICS

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DS12866 Rev 1

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HVLED007

Application information

a short while VCOMP falls again below VCOMP_BM in response to the energy burst and

stops again the IC, repeating the same sequence.

With this operating mode the duration of each burst and the idle time are automatically

adjusted according to the load conditions: as the load is progressively decreased, the

number of switching cycles in each burst becomes smaller and smaller and the duration

of the idle time becomes longer and longer. If the load increases, the number of switching

cycles in each burst becomes larger and the duration of the idle time becomes shorter,

until the operation becomes again continuous.

4.6

Multiplier input for input voltage sensing (pin MULT)

The multiplier input (MULT) is intended to sense the rectified input voltage through a resistor

divider to provide a sinusoidal template to the multiplier and the ICS circuit.

The user needs to properly select the voltage gain of the resistor divider Kp. The selection

criterion is that Kp needs to be large enough so that the peak of the programming signal

Vcsref (θ) generated by the ICS circuit at the minimum input voltage can reach the range of

the clamp value Vcsmax with a level of VCOMP voltage lower than the overload detection

threshold VCOMP_OL (see "Section 4.5: Control input for isolated feedback and optocoupler

driving (pin COMP)"). The condition to fulfill is:

Equation 11

with Kv_min = Vinpk_min /VR. It is recommended that Kp be as close to the value given by

(Equation 11) as possible (compatibly with expected tolerance of Kp), so as to maximize the

usage of the regulation range of VCOMP.

It is also recommended to check that with the selected Kp the amplitude of VMULTpk

calculated at the peak of the maximum specified input voltage does not exceed 3 V (linearity

limit of the multiplier), in which case the value of Kv_min should be increased (i.e. VR

reduced). Normally, this should not happen: the parameters of the ICS circuit have been

designed so as to allow a reflected voltage as high as 250 V even in an ultra-wide range

application (Vin = 85 to 305 Vac).

4.7

Current sensing input (pin CS). Sense resistor (Rs) selection

The PWM comparator (see Figure 4) senses the voltage Vcs (t, θ) across the current sense

resistor Rs and, by comparing it to the programming signal Vcsref (θ) generated by the ICS

circuit, determines the exact time when the external power switch is to be switched off, i.e.

Vcs (TON (θ), θ) = Vcsref (θ). Its output resets the PWM latch, previously set by the ZCD

triggering block (see Section 4.8: Zero current detection and triggering block (pin ZCD);

starter), which asserts the gate driver output low. The use of PWM latch avoids spurious

switching of the external power switch that might result from the noise generated ("double-

pulse suppression").

Cycle-by-cycle current limitation is realized by clamping the programming signal Vcsref (θ) at

a value Vcsmax (= 1.3 V typ.). The value of Vcsmax, along with that of the sense resistor Rs,

determines the overcurrent setpoint, i.e. the maximum peak current Ippk max allowed to flow

K p Vinpk_min = VMULT pk_min

Vcsmax_min

KM _min VCOMP_OL_min - VCOMPIo

 1+K

v_min



------------------------------------------------------------------------------------------------------------------------



1.231

1 Kv_min

-------------------------

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