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HVLED007 数据表(PDF) 22 Page - STMicroelectronics |
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HVLED007 数据表(HTML) 22 Page - STMicroelectronics |
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22 / 33 page ![]() Application information HVLED007 22/33 DS12866 Rev 1 Equation 15 where the last equality holds when Ct is selected as per proposed criterion. Whatever the design choice is, when designing the flyback transformer make sure that its saturation current Isat meets the condition: Equation 16 4.8 Zero current detection and triggering block (pin ZCD); starter The Zero Current Detection (ZCD) and Triggering blocks switch on the external MOSFET if a negative-going edge falling below 200 mV is applied to the ZCD pin. To do so, the triggering block must be previously armed by a positive-going edge exceeding 300 mV. The voltage at the pin is bottom limited by a clamp that holds the voltage on the pin close to zero during the ON-time of the external power switch. This arm/trigger operation is typically used to detect transformer demagnetization for TM operation, i.e. close to the boundary between the discontinuous and the continuous conduction mode. An intentional delay TR is added to the demagnetization detection instant to make the turn-on instant as close as possible to the point where the drain ringing is at a minimum (valley switching). The signal for the ZCD input is obtained from the transformer's auxiliary winding, typically used also to power the HVLED007. The triggering block is blanked for at least 1 μs after MOSFET's turn-off to prevent any negative-going edge that follows leakage inductance demagnetization from triggering the ZCD circuit erroneously (see "Section 4.9: Overload and short-circuit protection (OCP function)"). The interface between the pin and the auxiliary winding is a resistor divider. Its resistance ratio is properly chosen (see "Section 4.10: Overvoltage protection (OVP function)") and the upper resistance value Rzcd is such that the current sourced by the pin during the ON-time of the power switch is within the rated capability of the internal clamp (2.5 mA): Equation 17 where Npri and Naux are the primary and auxiliary turns number respectively. At converter power-up, as the IC exits from UVLO, no signal is coming from the ZCD pin, thus an internal oscillator ("Start Timer"), which is active as long as the gate driver (pin GD) is low, sets GD high as its timeout elapses and enables the converter to start up. Switching cycles is initiated by the internal starter until the output voltage and, then, the voltage Rs Vcsmax_min Ip pk_max -------------------------- 1 2 Rt Ct ------------ Lp Pin_max Kv_min VR 2 ---------------------------- – 1.14 Ip pk_max ---------------------- Isat Vcsmax_max Rs ---------------------------- = 1.4 Rs --------- Rzcd 400 N aux N pri ------------- Vinpk_max |
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