HVLED007 datasheet(28/33 Pages) STMICROELECTRONICS

28 / 33 page

Application information

HVLED007

28/33

DS12866 Rev 1

Calculate peak voltages corresponding to (Vin_min - Vin_max) and relevant Kv values

(Kv_min - Kv_max). Calculate estimated maximum input power Pin_max from max. load

and estimated efficiency:

Calculate operating conditions at Vin = Vin_min and Pin = Pin_max with the aid of the

equations in Table 8, using previously calculated values of Kv_min and Pin_max.

Calculate transformer's primary-to-secondary turns ratio, based on the desired VR:

Calculate required primary inductance from equation #3 in Table 6 solved for Lp and

with sin θ = 1, Kv = Kv_min and Pin = Pin_max:

Calculate first-cut value of shaping capacitor from (Equation 10) with sin θ = 1. This

value might be subject to post-design changes to optimize THD of input current or

adjust maximum deliverable power.

Pick maximum primary peak current Ippk_max; select sense resistor Rs using either

(Equation 14) or (Equation 15) and calculate required transformer saturation current

Isat from (Equation 16).

Design transformer with any commonly used procedure using data calculated in steps

2 to 6.

Calculate worst-case voltage stress on power switch and secondary rectifier from spec

data and actual primary-to-secondary turns ratio.

Select primary MOSFET and secondary rectifier using information on their current and

voltage stress derived in steps 3 and 7.

10. Use either output voltage ripple or AC current rating, whichever gives the higher

capacitance value, to select output capacitor Cout.

11. Calculate resistor divider connected to ZCD pin of HVLED007: determine Rzcd from

(Equation 17), then calculate Rovp with (Equation 18).

12. Determine multiplier bias gain Kp; pick a value larger than the minimum provided by

(Equation 11).:

check that the resulting amplitude of VMULTpk at Vin = Vin_max does not exceed 3 V; if it does,

Kv_min needs increasing (i.e. VR needs lowering) and design should restart from step 1.

Individual values of RmultH and RmultL may be selected based on power consumption

considerations.

13. Design clamp circuit that limits leakage inductance spikes with any commonly used

procedure with data calculated in step 2.

14. Design feedback circuit and its frequency compensation according to relevant

specifications (not included in Table 9 for simplicity).

Pin_max =

Vout Iout_max



--------------------------------

n =

N pri

N sec

-----------=

V out + VF

-------------------------

Lp = 1

---

f sw_min Pin_max

--------------------------------------

Kv_min

1+Kv_min

-----------------------





1.231

V inpk_min (1+Kv_min 

----------------------------------------------------



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