Data Sheet

ADRF5301

THEORY OF OPERATION

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Rev. 0 | 8 of 10

The ADRF5301 integrates a driver to perform logic functions inter-

nally and to provide the user with the advantage of a simplified

control interface. The driver features a single digital control input

pin, CTRL, which controls the state of the RF paths. The logic level

applied to the CTRL pin determines which RF port is in the insertion

loss state while the other path is in the isolation state (see Table 7).

RF INPUT AND OUTPUT

All of the RF ports (RFC, RF1, and RF2) are DC-coupled to 0 V,

and no DC blocking is required at the RF ports when the RF line

potential is equal to 0 V.

The RF ports are internally matched to 50 Ω. Therefore, external

matching networks are not required.

The ADRF5301 is bidirectional with equal power handling capabili-

ties. The RF input signal can be applied to the RFC port or the

selected RF throw port.

The insertion loss path conducts the RF signal between the select-

ed RF throw port and the RF common port. The isolation paths

provide high loss between the insertion loss path and the unselect-

ed RF throw port that is reflective.

POWER SUPPLY

The ADRF5301 integrates a negative voltage generator (NVG)

and requires a single positive supply voltage applied to the VDD

pin. Bypassing capacitors are recommended on the supply line to

minimize RF coupling.

The ideal power-up sequence is as follows:

1. Connect GND reference.

2. Power-up supply input VDD.

3. Apply digital control input CTRL. Applying the CTRL control

before applying the VDD supply inadvertently forward biases

and damages the internal ESD protection structures. To avoid

this damage, use a series 1 kΩ resistor to limit the current

flowing into the control pin. Use pull-up or pull-down resistors if

the controller output is in a high-impedance state after VDD is

powered up and the control pins are not driven to a valid logic

state.

4. Apply RF input signal.

The ideal power-down sequence is the reverse order of the power-

up sequence.

TIMING REQUIREMENTS

There are timing requirements for the proper operation of the bias

and control circuits. See Table 2 for the timing specifications. See

Figure 13 for the timing requirements.

After VDD reaches the operating range, tPOWERUP defines the wait

time before the recommended maximum RF power can be applied.

During this time, a maximum of 10 dBm RF input power can be

applied.

The minimum wait time before switching states is defined by tHOLD.

The maximum rise and fall time of the CTRL pulse is defined by

tSLEW.

Figure 13. Timing Requirements

Table 7. Control Voltage Truth Table

Digital Control Input

RF Paths

CTRL

RF1 to RFC

RF2 to RFC

High

Insertion loss (on)

Isolation (off)

Low

Isolation (off)

Insertion loss (on)