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F4MP 数据表(PDF) 5 Page - NXP Semiconductors |
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F4MP 数据表(HTML) 5 Page - NXP Semiconductors |
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5 / 37 page ![]() PTN3355 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 3.1 — 4 November 2016 5 of 37 NXP Semiconductors PTN3355 Low power DP to VGA adapter with integrated 1 : 2 VGA switch 6. Pinning information 6.1 Pinning 6.2 Pin description (1) Exposed die pad. Fig 2. Pin configuration for HVQFN40 002aag884 PTN3355BS VDDE33_IO ML1_P ML1_N DDC_SDA1 VDDA15_DP DDC_SCL2 ML0_N VSYNC1 ML0_P HSYNC1 VDDE33_IO BLU1 AUX_N BLU2 AUX_P GRN1 DOCK_IN GRN2 VDDA33_DNW RSET 10 21 9 22 8 23 7 24 6 25 5 26 4 27 3 28 2 29 1 30 terminal 1 index area Transparent top view GND(1) Table 3. Pin description Symbol Pin Type Description VDDA33_DNW 1 power 3.3 V power supply DOCK_IN 2 3.3 V digital I/O Docked indication signal AUX_P 3 self-biasing differential input DisplayPort AUX channel positive input AUX_N 4 self-biasing differential input DisplayPort AUX channel negative input VDDE33_IO 5 power 3.3 V power supply for I/O ML0_P 6 self-biasing differential input DisplayPort Main Link lane 0 positive input ML0_N 7 self-biasing differential input DisplayPort Main Link lane 0 negative input VDDA15_DP 8 power 1.5 V power supply for DisplayPort PHY; power provided to this pin from SWOUT pin ML1_P 9 self-biasing differential input DisplayPort Main Link lane 1 positive input |
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