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F4MP 数据表(PDF) 6 Page - NXP Semiconductors |
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F4MP 数据表(HTML) 6 Page - NXP Semiconductors |
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6 / 37 page ![]() PTN3355 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved. Product data sheet Rev. 3.1 — 4 November 2016 6 of 37 NXP Semiconductors PTN3355 Low power DP to VGA adapter with integrated 1 : 2 VGA switch [1] HVQFN40 package die supply ground is connected to exposed center pad. Exposed center pad must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad must be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias must be incorporated in the PCB in the thermal pad region. ML1_N 10 self-biasing differential input DisplayPort Main Link lane 1 negative input RST_N 11 3.3 V digital input Reset input active LOW; pulled up to VDD(3V3) internally DDC_SDA2 12 5 V open-drain I/O DDC I2C-bus data for channel 2 HPD 13 3.3 V digital I/O DisplayPort Hot Plug Detection output CFG1_SCL 14 5 V open-drain I/O General purpose configuration pin CFG1 or slave I2Cclock CFG5 15 3.3 V digital I/O Configuration pin supporting trinary input CFG3 16 3.3 V digital I/O Reserved CFG2_SDA 17 5 V open-drain I/O General purpose configuration pin CFG2 or slave I2Cdata VSYNC2 18 3.3 V 50 digital I/O Vertical sync for channel 2 HSYNC2 19 3.3 V 50 digital I/O Horizontal sync for channel 2 DDC_SCL1 20 5 V open-drain I/O DDC I2C-bus clock for channel 1 VDDE33_IO 21 power 3.3 V power supply for I/O DDC_SDA1 22 5 V open-drain I/O DDC I2C-bus data for channel 1 DDC_SCL2 23 5 V open-drain I/O DDC I2C-bus clock for channel 2 VSYNC1 24 3.3 V 50 digital I/O Vertical sync for channel 1 HSYNC1 25 3.3 V 50 digital I/O Horizontal sync for channel 1 BLU1 26 analog output Blue DAC analog output for channel 1 BLU2 27 analog output Blue DAC analog output for channel 2 GRN1 28 analog output Green DAC analog output for channel 1 GRN2 29 analog output Green DAC analog output for channel 2 RSET 30 input Resistor for DAC output reference control RED1 31 analog output Red DAC analog output for channel 1 RED2 32 analog output Red DAC analog output for channel 2 OSC_IN 33 input Crystal oscillator input OSC_OUT 34 output Crystal oscillator output VDDA15_DAC 35 power 1.5 V power supply for DAC; power provided to this pin from SWOUT pin VDDD15 36 power 1.5 V power supply for digital core; power provided to this pin from SWOUT pin TESTMODE 37 input Test mode selection for CFG/JTAG and I2C slave address selection; supports trinary input PVDD33 38 power 3.3 V power supply for switching regulator SWOUT 39 power Switching regulator output PGND 40 ground Ground for switching regulator GND[1] - power central supply ground connection (exposed die pad) Table 3. Pin description …continued Symbol Pin Type Description |
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