PTN3355

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© NXP Semiconductors N.V. 2016. All rights reserved.

Product data sheet

Rev. 3.1 — 4 November 2016

12 of 37

NXP Semiconductors

PTN3355

Low power DP to VGA adapter with integrated 1 : 2 VGA switch

The TESTMODE pin is used to indicate selection of JTAG or Configuration/I2C mode for

CFG1_SCL, CFG2_SDA and CFG5. Table 7 defines the possible combinations of

TESTMODE pin.

CFG1_SCL, CFG2_SDA can be used in I2C mode or configuration pin mode. PTN3355

automatically detects the mode in which these pins are used. If they are used as

Configuration pins, Table 8 determines the possible and allowed combinations for these

pin settings. If they are used as I2C Clock/Data pins, PTN3355 detects toggling of the pins

during I2C data transport and receives data properly.

More configuration options are available through internal configuration registers. These

registers can be accessed by GPU/CPU software driver via DP AUX channel or I2C-bus.

NXP can deliver Windows and DOS based utilities, on explicit request, to upgrade the

firmware or configuration registers only for laboratory evaluation and debugging purposes

at customer premises.

10. Application design-in information

With its maximum integration features, the PTN3355 has low BOM requirement at the

platform application level. Figure 4 illustrates the PTN3355 usage in a system application

context. On the DP side, it is connected to DP source and the VGA side, it is connected to

VGA connector. The PTN3355 system application requires the following components

additionally: supply decoupling capacitors, DC blocking capacitors, pull-up/down resistors,

(optional) inductor for DC-to-DC converter, crystal oscillator. For more details on reference

design information, contact NXP team.

Table 7.

TESTMODE pin definition

Pin value

Mode selection

LOW

Configuration pin functionality is selected; I2C address for

CFG1_SCL, CFG2_SDA is 40h.

open

Configuration pin functionality is selected; I2C address for

CFG1_SCL, CFG2_SDA is C0h.

HIGH

JTAG functionality is selected.

Table 8.

CFG1_SCL/CFG2_SDA pin definitions

Pin value

System behavior

00

Compliant HPD behavior

01

Most interoperable (non-compliant) HPD behavior

10

Most interoperable (non-compliant) HPD behavior

11

(Default) Compliant behavior (but configurable via I2C-bus)