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STLC2500ATR 数据表(PDF) 11 Page - STMicroelectronics |
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STLC2500ATR 数据表(HTML) 11 Page - STMicroelectronics |
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11 / 37 page  STLC2500A Pinout 11/37 4 Pinout 4.1 Pin assignment Figure 2. STLC2500A pin assignment (bottom view) 4.2 Pin description and assignment Table 12 shows the pin list of the STLC2500A.The column "PU/PD" shows the pads implementing a pull-down/up. The column "DIR" describes the pin directions: – I for inputs – O for outputs – I/O for input/output – O/t for tri-state outputs ABUS_ QP_IP ANA_1 ABUS_ IN_QN VSS_RF RFN RFP VSS_RF VDD_HV VSS_ANA VSS_DIG VSS_ANA VSS_ANA ABUS_ QN_IN ABUS_ IP_QP VSS_ ANA VDD_RF ANA_2 VSS_ANA VDD_DIG JTAG_TDO ANA_3 VSS_ANA VSS_ANA VDD_T VSS_ANA VSS_ANA JTAG_ NTRST JTAG_TDI VDD_DSM VSS_ANA VSS_ANA ANA_4 VSS_ANA VSS_DIG VSS_DIG JTAG_TCK JTAG_TMS PCM_SYNC PCM_CLK VDD_N VDD_HV VSS_ANA VDD_IO_A PCM_A PCM_B VDD_CL VSS_ANA VDD_CLD VSS_DIG VDD_IO_A VDD_IO_A RF_CLK_IN VDD_CLD VSS_DIG VSS_DIG VSS_DIG VSS_DIG VSS_DIG CONFIG _R CONFIG _CLK CONFIG _JS VDD_DIG GPIO_2 GPIO_0 UART_ RXD UART_ CTS HOST_ WAKEUP CONFIG _RF BT_ WAKEUP VDD_DIG CONFIG _M AF_PRG GPIO_3 PGIO_1 UART_ TXD UART_ RTS LP_CLK VDD_IO_B RESETN VDD_D VDD_HV VDD_HV VDD_DIG VDD_HV A B C D E F G H J K 10 9 8 7 6 5 4 3 2 1 |
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