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STLC2500ATR 数据表(PDF) 31 Page - STMicroelectronics |
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STLC2500ATR 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 37 page ![]() STLC2500A Digital interfaces 31/37 Figure 10. PCM (A-law, µ-law) standard mode Figure 11. Linear mode Figure 12. Multi-slot operation The PCM implementation supports from 1 up to 3 slots per frame with the following parameters: Table 20. PCM interface parameters Symbol Parameter Min. Typ. Max. Unit PCM interfaces FPCM_CLK Frequency of PCM_CLK 140 (1) 2048 4000 kHz FPCM_SYNC Frequency of PCM_SYNC 8 kHz Psync_delay Delay of the starting of the first slot 0 255 cycles Pclk_number PCM_CLK is available during this number of clock cycles 0 255 cycles 0 1 15 PCM_CLK 125 µs PCM_SYNC PCM_A PCM_B D02TL559 PCM_CLK PCM_SYNC PCM_A PCM_B 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 125 µs |
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