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STLC2500ATR 数据表(PDF) 12 Page - STMicroelectronics

部件名 STLC2500ATR
功能描述  Bluetooth Single Chip
PDF  37 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STLC2500ATR 数据表(HTML) 12 Page - STMicroelectronics

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Pinout
STLC2500A
12/37
The column Reset and Default show the state of the pins in reset and the default value after
reset. For the output pin the default drive capability is 2 mA.
Table 12.
STLC2500A pin list (functional and supply)
Name
Pin #
Description
DIR
Reset
Default
after
reset
VDD_
IO_x
Clock and reset pins
RESETN
K03
Global reset - active low
I
Input
Input
A
RF_CLK_IN
H10
Reference clock input
I
Input
Input
(1)
LP_CLK
K05
Low power clock input
I
Input
Input
B
SW initiated low power mode
HOST_
WAKEUP
J05
Wake-up signal to host
(Open drain output)
I/O
Input PD
Output
high
A
BT_WAKEUP
J03
Wake-up signal to Bluetooth
I
Input(2)
Input
A
UART interface
UART_RXD
J07
UART receive data
I
Input PD
Input
A
UART_TXD
K07
UART transmit data
O/t (I/O)
Tri-state
PD
Output
high
A
UART_CTS
J06
UART clear to send
I
Input PU
(2)
Input
A
UART_RTS
K06
UART Request to send
O/t (I/O)
Tri-state
PU
Output
low
A
PCM interface
PCM_SYNC
E02
PCM frame signal
I/O
Input PD Input PD
A
PCM_CLK
E01
PCM clock signal
I/O
Input PD Input PD
A
PCM_A
F02
PCM data
I/O
Input PD Input PD
A
PCM_B
F01
PCM data
I/O
Input PD Input PD
A
JTAG interface
JTAG_TDI
C01
JTAG data input
I
Input PU Input PU
A
JTAG_TDO
B01
JTAG data output
O/t
Tri-state
Tri-state
A
JTAG_TMS
D01
JTAG mode signal
I
Input PU Input PU
A
JTAG_NTRST
C02
JTAG reset active low
I
Input PD Input PD
A
JTAG_TCK
D02
JTAG clock input
I
Input(3)
Input
A
General purpose Input/Output pins
GPIO_0
J08
General purpose IO
I/O
Input PD Input PD
A
GPIO_1
K08
General purpose IO
I/O
Input PD Input PD
A
GPIO_2
J09
General purpose IO
I/O
Input PD Input PD
A
GPIO_3
K09
General purpose IO
I/O
Input PD Input PD
A



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