STLC2500ATR datasheet(15/37 Pages) STMICROELECTRONICS

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STLC2500A

Pinout

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Configuration pins

The configuration pins are used to select different modes of operation for the chip:

Where '1' means VDD_IO_A and '0' means VSS_DIG.

The other two configuration pins, CONFIG_RF and CONFIG_R have to be strapped to

VSS_DIG.

Table 13.

STLC2500A pin list (test)

Name

Pin #

Description

DIR

Reset

Default

VDDIO

Analogue test pin

VDD_T

C06

Test supply

ABUS_IN_QN

A08

Test pin

I/O

Input(1)

To be strapped to VSS_ANA

Input (1)

ABUS_QP_IP

A09

Test pin

I/O

Input (1)

ABUS_IP_QP

B07

Test pin

I/O

Input (1)

ABUS_QN_IN

B08

Test pin

I/O

Input (1)

ANA_1

A10

Analogue test pin

(Leave unconnected)

ANA_2

B04

Analogue test pin

(Leave unconnected)

ANA_3

C10

Analogue test pin

(Leave unconnected)

ANA_4

D09

Analogue test pin

(Leave unconnected)

AF_PRG

K10

Test pin (Leave unconnected)

I/O

Open

Table 14.

STLC2500A configuration pins

Configuration

Description

Digital or analogue incoming system clock

CONFIG_CLK =’1’

The incoming system clock is a digital square signal.

(See

Section 2.4)

CONFIG_CLK =’0’

The incoming system clock is a sine wave signal.

(See

Section 2.4)

Initiated deep sleep modes

CONFIG_JS =’0’ AND

CONFIG_M = ‘0’

Reserved

CONFIG_JS =’0’ AND

CONFIG_M = ‘1’

Initiated Deep Sleep, mode 1. (See

Section 6.8)

CONFIG_JS =’1’ AND

CONFIG_M = ‘0’

Initiated Deep Sleep, mode 2. (See

Section 6.8)

CONFIG_JS =’1’ AND

CONFIG_M = ‘1’

Reserved

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