 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
TDA4AL...ALZQ1 数据表(PDF) 110 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
TDA4AL...ALZQ1 数据表(HTML) 110 Page - Texas Instruments |
|
|
110 / 251 page  Over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH Output High Voltage 2.4 V IOL Low Level Output Current VOL(MAX) 5 mA IOH High Level Output Current VOH(MIN) 6 mA (1) VDD stands for corresponding power supply. For more information on the power supply name and the corresponding ball, see the Pin Attributes, POWER column. 7.6.9 USB2PHY Electrical Characteristics Note USB0 and USB1 Electrical Characteristics are compliant with Universal Serial Bus Revision 2.0 Specification dated April 27, 2000 including ECNs and Errata as applicable. 7.6.10 SerDes 2-L-PHY/4-L-PHY Electrical Characteristics Note The PCIe interfaces are compliant with the electrical parameters specified in PCI Express® Base Specification Revision 4.0, September 27, 2017. This Device imposes an additional limit on SERDES REFCLK when used in Input mode with internal termination enabled, as described by parameter VREFCLK_TERM in Table 7-2, 4-L-PHY SERDES REFCLK Electrical Characteristics. Internal termination is enabled by default and must be disabled before applying a reference clock signal that exceeds the limits defined by VREFCLK_TERM. External termination should always be enabled on the source side. Table 7-2. 4-L-PHY SERDES REFCLK Electrical Characteristics Only applies when internal termination is enabled. Over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP MAX UNIT VREFCLK_TER M Single ended voltage threshold at the reference clock pin when internal termination is enabled 400 mV RTERM Internal termination 40 50 62.5 Ω Note The SerDes USB interfaces are compliant with the USB3.1 SuperSpeed Transmitter and Receiver Normative Electrical Parameters as defined in the Universal Serial Bus 3.1 Specification, Revision 1.0 , July 26, 2013. Note The SGMII interfaces electrical characteristics are compliant with 1000BASE-KX per IEEE802.3 Clause 70. Note The SGMII 2.5G / XAUI interfaces electrical characteristics are compliant with IEEE802.3 Clause 47. Note The QSGMII interface electrical characteristics are compliant with QSGMII Specification revision 1.2. TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1 SPRSP62 – DECEMBER 2022 www.ti.com 110 Submit Document Feedback Copyright © 2023 Texas Instruments Incorporated Product Folder Links: TDA4VE-Q1 TDA4AL-Q1 TDA4VL-Q1 |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
