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7.10.2 Power Supply Sequencing

This section describes power supply sequencing required to ensure proper device operation. The device can be

operated using either an isolated or combined MCU & Main power distribution network (PDN). Two different

primary power sequences are recommended based upon isolated and combined MCU & Main PDNs. In

addition, the device can be operated in either MCU Only or DDR Retention or GPIO Retentioon low power

modes. Two different desired device power supply sequences for entry and exit of low power modes are shown.

The power supply names used in this section are specific to this device and align to names given in the Signal

Descriptions section. Common power supply names may be used across different devices within the Jacinto 7TM

processor family. These common supply names will have very similar if not identical functions across devices.

All power sequencing timing diagrams shown will use the following terminology:

• Primary = Essential power sequences of all voltage domains between off and full active states.

• VOPR MIN = Minimum operational voltage level that ensures functionality as specified in Recommended

Operating Conditions

• Ramp-up = start of a voltage supply transition time from off condition to Vopr min.

• Ramp-down = start of a voltage supply transition time from Vopr to off condition

• Supply_“n” = multiple instances of similar power supplies (i.e. VDDSHVn = VDDSHV0, VDDSHV1,

VDDSHV2 … VDDSHV6)

• Supply_“xxx” = multiple instances of similar power supplies used for different signal types (i.e.

VDDA_1P8_xxx = VDDA_1P8_DSITX, VDDA_1P8_USB, VDDA_0P8_DSITX, VDDA_0P8_USB, etc.)

• Time stamps = “T#” markers with descriptions and approximate elapsed times for general reference. Specific

timing transitions are dependent upon PDN design (see PDN User Guide for details).

7.10.2.1 Power Supply Slew Rate Requirement

To maintain the safe operating range of the internal ESD protection devices, TI recommends limiting the

maximum slew rate of supplies to be less than 100 mV/us, as shown in Figure 7-2. For instance, a 1.8V supply

should have a ramp time > 18 μs to ensure the slew rate < 100mV/us.

Figure 7-2 describes the Power Supply Slew Rate Requirement in the device.

Supply value

SPRSP08_ELCH_06

Slew Rate = ∆V / ∆T

Max Slew Rate < 100 mV / µs or 0.1 V / 1E(-6)s = 1E(+5) V / s

∆Tmin > ∆V / Max Slew Rate or 1.8 V / 1E(+5) V / s

∆Tmin > 18 µs

Figure 7-2. Power Supply Slew and Slew Rate

TDA4VE-Q1, TDA4AL-Q1, TDA4VL-Q1

SPRSP62 – DECEMBER 2022

www.ti.com

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