KSZ9563RNXI datasheet(106/226 Pages) MICROCHIP

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KSZ9563R

DS00002419D-page 106

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5.1.6

GLOBAL SWITCH PTP CONTROL REGISTERS (0x0500 - 0x05FF)

5.1.6.1

Global PTP Clock Control Register

Address:

0x0500 - 0x0501

Size:

16 bits

Bits

Description

Type

Default

Disable Switch Frequency Adjustment

1 = The switch timers, shapers and policing logic will NOT adjust the

frequency based on PTP adjustments.

0 = The switch timers, shapers and policing logic will adjust the frequency

based on PTP adjustments.

R/W

14:7

RESERVED

000_0000_0b

PTP Clock Step Adjustment

Setting this bit will cause the time value in the Global PTP RTC Clock

Nanosecond High Word Register and Global PTP RTC Clock Nanosecond

High Word Register to be added to or subtracted from (based on the value of

bit 5) the PTP clock.

R/W

PTP Step Direction

Direction control for PTP step adjustment mode.

1 = Add the time value

0 = Subtract the time value

R/W

PTP Clock Read

Setting this bit will cause the current PTP clock value to be copied into

registers 0x0502 to 0x050B.

R/W

PTP Clock Load

Setting this bit will cause the PTP clock to be loaded with the time value in

registers 0x0502 to 0x050B.

R/W

PTP Clock Continuous Adjustment

When continuous adjustment is enabled, the SUB-NS_RATE value in the

Global PTP Clock Sub-Nanosecond Rate High Word Register and Global

PTP Clock Sub-Nanosecond Rate Low Word Register is added to or

subtracted from (based on the PTP_RATE_DIR bit in the Global PTP Clock

Sub-Nanosecond Rate High Word Register) the PTP clock on every 25MHz

clock cycle.

1 = Enable continuous adjustment

0 = Disable continuous adjustment

R/W

Enable PTP Clock

1 = Enable PTP clocking

0 = Disable PTP clocking

R/W

Reset PTP Clock

Setting this bit will reset the PTP clock.

R/W

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