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KSZ9563RNXI 数据表(PDF) 109 Page - Microchip Technology |
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KSZ9563RNXI 数据表(HTML) 109 Page - Microchip Technology |
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109 / 226 page  2017-2018 Microchip Technology Inc. DS00002419D-page 109 KSZ9563R 5.1.6.9 Global PTP Clock Temp Adjustment Duration High Word Register 5.1.6.10 Global PTP Clock Temp Adjustment Duration Low Word Register 5.1.6.11 Global PTP Message Config 1 Register Address: 0x0510 - 0x0511 Size: 16 bits Bits Description Type Default 15:0 PTP Temporary Adjustment Duration [31:16] This sets the duration for the PTP clock temporary rate adjustment, in number of 25MHz clock cycles. R/W 0x0000 Address: 0x0512 - 0x0513 Size: 16 bits Bits Description Type Default 15:0 PTP Temporary Adjustment Duration [15:0] This sets the duration for the PTP clock temporary rate adjustment, in number of 25MHz clock cycles. R/W 0x0000 Address: 0x0514 - 0x0515 Size: 16 bits Bits Description Type Default 15:7 RESERVED RO 0x00 6 Enable IEEE 1588 PTP Mode 1 = enable 0 = disable R/W 0b 5 Enable Detection of IEEE 802.3 Ethernet PTP Messages 1 = enable 0 = disable R/W 1b 4 Enable Detection of IPv4/UDP PTP Messages 1 = enable 0 = disable R/W 1b 3 Enable Detection of IPv6/UDP PTP Messages 1 = enable 0 = disable R/W 1b 2 Selection of P2P or E2E 1 = Peer-to-peer (P2P) transparent clock mode 0 = End-to-end (E2E) transparent clock mode R/W 0b |
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