5.1.3

Write identification page (M2512-D only)

The identification page (128 byte) is an additional page which can be written and (later) permanently locked in

read-only mode. It is written by issuing the write identification page instruction. This instruction uses the same

protocol and format as page write (into memory array), except for the following differences:

•

Device type identifier = 1011b

•

MSB address bits A15/A7 are don't care except for address bit A10 which must be ‘0’. LSB address bits

A6/A0 define the byte address inside the identification page.

If the identification page is locked, the data bytes transferred during the write identification page instruction are not

acknowledged (NoAck).

5.1.4

Lock identification page (M24512-D only)

The lock identification page instruction (Lock ID) permanently locks the identification page in read-only mode. The

lock ID instruction is similar to byte write (into memory array) with the following specific conditions:

•

Device type identifier = 1011b

•

Address bit A10 must be ‘1’; all other address bits are don't care

•

The data byte must be equal to the binary value xxxx xx1x, where x is don't care

5.1.5

ECC (error correction code) and write cycling

The error correction code (ECC) is an internal logic function which is transparent for the I2C communication

protocol.

The ECC logic is implemented on each group of four EEPROM bytes (A group of four bytes is located at

addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). Inside a group, if a single bit out of the four bytes

happens to be erroneous during a read operation, the ECC detects this bit and replaces it with the correct value.

The read reliability is therefore much improved.

Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently.

In this case, the ECC function also writes/cycles the three other bytes located in the same group (A group of four

bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). As a consequence, the

maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group:

the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum

value defined Table 12. Cycling performance by groups of four bytes.

M24512-W M24512-R M24512-DF

Write operations

DS6520 - Rev 31

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