Table 16. 100 kHz AC characteristics (I2C standard-mode)

Symbol

Alt.

Parameter

Min.

Max.

Unit

fC

fSCL

Clock frequency

-

100

kHz

tCHCL

tHIGH

Clock pulse width high

4

-

μs

tCLCH

tLOW

Clock pulse width low

4.7

-

μs

tXH1XH2

tR

Input signal rise time

-

1

μs

tXL1XL2

tF

Input signal fall time

-

300

ns

tQL1QL2(1)

tF

SDA (out) fall time

-

300

ns

tDXCH

tSU:DAT

Data in setup time

250

-

ns

tCLDX

tHD:DAT

Data in hold time

0

-

ns

tCLQX(2)

tDH

Data out hold time

200

-

ns

tCLQV(3)

tAA

Clock low to next data valid (access time)

-

3450

ns

tCHDL(4)

tSU:STA

Start condition setup time

4.7

-

μs

tDLCL

tHD:STA

Start condition hold time

4

-

μs

tCHDH

tSU:STO Stop condition setup time

4

-

μs

tDHDL

tBUF

Time between Stop condition and next Start condition

4.7

-

μs

tW

tWR

Write time

-

5

ms

tNS(1)

-

Pulse width ignored (input filter on SCL and SDA), single glitch

-

100

ns

1. Evaluated by characterization - Not tested in production.

2. To avoid spurious start ands top conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of

SDA.

3. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming

that the Rbus × Cbus time constant is within the values specified in Figure 11.

4. For a reStart condition, or following a write cycle.

M24C01/02-W M24C01/02-R M24C02-F

DC and AC parameters

DS9398 - Rev 7

page 24/41