5.3

Hold condition

The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking

sequence.

To enter the Hold condition, the device must be selected, with Chip select (S) low.

During the Hold condition, the Serial data output (Q) is high impedance, and the Serial data input (D) and the

Serial clock (C) are Don’t care.

Normally, the device is kept selected for the whole duration of the Hold condition. Deselecting the device while it

is in the Hold condition has the effect of resetting the state of the device: this mechanism can be used, if required,

to reset the ongoing processes.

Note:

This resets the internal logic, except the WEL and WIP bits of the Status register.

In the specific case where the device has moved in a Write command (Inst + Address + data bytes, each data

byte being exactly 8 bits), deselecting the device also triggers the Write cycle of this decoded command.

Figure 7. Hold condition activation

Hold

condition

Hold

condition

HOLD

C

The Hold condition starts when the Hold (HOLD) signal is driven low when Serial clock (C) is already low (as

shown in Figure 7. Hold condition activation).

Figure 7. Hold condition activation also shows what happens if the rising and falling edges are not timed to

coincide with Serial clock (C) being low.

5.4

Status register

The Status register contains a number of status and control bits that can be read or set (as appropriate) by

specific instructions. See Section 6.3 Read Status register (RDSR) for a detailed description of the Status

register bits.

M95128-W M95128-R M95128-DF

Hold condition

DS1356 - Rev 20

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