The Write Status register (WRSR) instruction enables the user to change the values of the BP1, BP0 and SRWD

bits:

•

The Block protect (BP1, BP0) bits define the size of the area that is to be treated as read-only, as defined in

Table 3. Write-protected block size.

•

The SRWD (Status register Write Disable) bit, in accordance with the signal read on the Write protect pin

(W), enables the user to set or reset the Write protection mode of the Status register itself, as defined in

Table 7. Protection modes. When in Write-protected mode, the Write Status register (WRSR) instruction is

not executed.

The contents of the SRWD and BP1, BP0 bits are updated after the completion of the WRSR instruction,

including the tW Write cycle.

The Write Status register (WRSR) instruction has no effect on the b6, b5, b4, b1, b0 bits in the Status register.

Bits b6, b5, b4 are always read as 0.

Table 7. Protection modes

W signal

SRWD

bit

Mode

Write protection of the Status register

Memory content

Protected

area (1)

Unprotected area(1)

1

0

Software-

protected

(SPM)

Status register is writable (if the WREN

instruction has set the WEL bit).

The values in the BP1 and BP0 bits can be

changed.

Write-

protected

Ready to accept

Write instructions

0

0

1

1

0

1

Hardware-

protected

(HPM)

Status register is Hardware write-protected.

The values in the BP1 and BP0 bits cannot be

changed.

Write-

protected

Ready to accept

Write instructions

1. As defined by the values in the Block protect (BP1, BP0) bits of the Status register. See Table 3. Write-protected block size.

The protection features of the device are summarized in Table 7.

When the Status register Write Disable (SRWD) bit in the Status register is 0 (its initial delivery state), it is

possible to write to the Status register (provided that the WEL bit has previously been set by a WREN instruction),

regardless of the logic level applied on the Write protect (W) input pin.

When the Status register Write Disable (SRWD) bit in the Status register is set to 1, two cases should be

considered, depending on the state of the Write protect (W) input pin:

•

If Write protect (W) is driven high, it is possible to write to the Status register (provided that the WEL bit has

previously been set by a WREN instruction).

•

If Write protect (W) is driven low, it is not possible to write to the Status register even if the WEL bit has

previously been set by a WREN instruction. (Attempts to write to the Status register are rejected, and are not

accepted for execution). As a consequence, all the data bytes in the memory area, which are Software-

protected (SPM) by the Block protect (BP1, BP0) bits in the Status register, are also hardware-protected

against data modification.

Regardless of the order of the two events, the Hardware-protected mode (HPM) can be entered by:

•

either setting the SRWD bit after driving the Write protect (W) input pin low,

•

or driving the Write protect (W) input pin low after setting the SRWD bit.

Once the Hardware-protected mode (HPM) has been entered, the only way of exiting it is to pull high the Write

protect (W) input pin.

If the Write protect (W) input pin is permanently tied high, the Hardware-protected mode (HPM) can never be

activated, and only the Software-protected mode (SPM), using the Block protect (BP1, BP0) bits in the Status

register, can be used.

M95128-W M95128-R M95128-DF

Write Status register (WRSR)

DS1356 - Rev 20

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