P80C32 datasheet(33/62 Pages) PHILIPS

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Philips Semiconductors

Product data

P80C3xX2; P80C5xX2;

P87C5xX2

80C51 8-bit microcontroller family

4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),

low power, high speed (30/33 MHz)

2003 Jan 24

Interrupt Priority Structure

IE0

IE1

INT0

IT0

TF0

INT1

IT1

TF1

Interrupt

Sources

SU01521

TF2, EXF2

Figure 21. Interrupt Sources

Interrupts

The devices described in this data sheet provide six interrupt

sources. These are shown in Figure 21. The External Interrupts

INT0 and INT1 can each be either level-activated or

transition-activated, depending on bits IT0 and IT1 in Register

TCON. The flags that actually generate these interrupts are bits IE0

and IE1 in TCON. When an external interrupt is generated, the flag

that generated it is cleared by the hardware when the service routine

is vectored to only if the interrupt was transition-activated. If the

interrupt was level-activated, then the external requesting source is

what controls the request flag, rather than the on-chip hardware.

The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1,

which are set by a rollover in their respective Timer/Counter

registers (except see Timer 0 in Mode 3). When a timer interrupt is

generated, the flag that generated it is cleared by the on-chip

hardware when the service routine is vectored to.

The Serial Port Interrupt is generated by the logical OR of RI and TI.

Neither of these flags is cleared by hardware when the service

routine is vectored to. In fact, the service routine will normally have

to determine whether it was RI or TI that generated the interrupt,

and the bit will have to be cleared in software.

All of the bits that generate interrupts can be set or cleared by

software, with the same result as though it had been set or cleared

by hardware. That is, interrupts can be generated or pending

interrupts can be canceled in software.

Each of these interrupt sources can be individually enabled or

disabled by setting or clearing a bit in Special Function Register IE

(Figure 22). IE also contains a global disable bit, EA, which disables

all interrupts at once.

Priority Level Structure

Each interrupt source can also be individually programmed to one of

four priority levels by setting or clearing bits in Special Function

Registers IP (Figure 23) and IPH (Figure 24). A lower-priority

interrupt can itself be interrupted by a higher-priority interrupt, but

not by another interrupt of the same level. A high-priority level 3

interrupt can’t be interrupted by any other interrupt source.

If two request of different priority levels are received simultaneously,

the request of higher priority level is serviced. If requests of the

same priority level are received simultaneously, an internal polling

sequence determines which request is serviced. Thus within each

priority level there is a second priority structure determined by the

polling sequence as follows:

Source

Priority Within Level

1. IE0 (External Int 0)

(highest)

2. TF0 (Timer 0)

3. IE1 (External Int 1)

4. TF1 (Timer 1)

5. RI+TI (UART)

6. TF2, EXF2 (Timer 2)

(lowest)

Note that the “priority within level” structure is only used to resolve

simultaneous requests of the same priority level.

The IP and IPH registers contain a number of unimplemented bits.

User software should not write 1s to these positions, since they may

be used in other 80C51 Family products.

How Interrupts Are Handled

The interrupt flags are sampled at S5P2 of every machine cycle.

The samples are polled during the following machine cycle. If one of

the flags was in a set condition at S5P2 of the preceding cycle, the

polling cycle will find it and the interrupt system will generate an

LCALL to the appropriate service routine, provided this

hardware-generated LCALL is not blocked by any of the following

conditions:

1. An interrupt of equal or higher priority level is already in

progress.

2. The current (polling) cycle is not the final cycle in the execution

of the instruction in progress.

3. The instruction in progress is RETI or any write to the IE or IP

registers.

Any of these three conditions will block the generation of the LCALL

to the interrupt service routine. Condition 2 ensures that the

instruction in progress will be completed before vectoring to any

service routine. Condition 3 ensures that if the instruction in

progress is RETI or any access to IE or IP, then at least one more

instruction will be executed before any interrupt is vectored to.

The polling cycle is repeated with each machine cycle, and the

values polled are the values that were present at S5P2 of the

previous machine cycle. Note that if an interrupt flag is active but not

being responded to for one of the above conditions, if the flag is not

still active when the blocking condition is removed, the denied

interrupt will not be serviced. In other words, the fact that the

interrupt flag was once active but not serviced is not remembered.

Every polling cycle is new.

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