P80C32 datasheet(35/62 Pages) PHILIPS

35 / 62 page

Philips Semiconductors

Product data

P80C3xX2; P80C5xX2;

P87C5xX2

80C51 8-bit microcontroller family

4K/8K/16K/32K ROM/OTP, low voltage (2.7 to 5.5 V),

low power, high speed (30/33 MHz)

2003 Jan 24

. . . .

Interrupts

Are Polled

Long Call to

Interrupt

Vector Address

Interrupt Routine

Interrupt

Goes

Active

. . . . . . . . .

Interrupt

Latched

This is the fastest possible response when C2 is the final cycle of an instruction other than RETI or an access to IE or IP.

S5P2

. . . . . . . . .

SU00546

Figure 25. Interrupt Response Timing Diagram

The polling cycle/LCALL sequence is illustrated in Figure 25.

Note that if an interrupt of higher priority level goes active prior to

S5P2 of the machine cycle labeled C3 in Figure 25, then in

accordance with the above rules it will be vectored to during C5 and

C6, without any instruction of the lower priority routine having been

executed.

Thus the processor acknowledges an interrupt request by executing

a hardware-generated LCALL to the appropriate servicing routine. In

some cases it also clears the flag that generated the interrupt, and in

other cases it doesn’t. It never clears the Serial Port flag. This has to

be done in the user’s software. It clears an external interrupt flag

(IE0 or IE1) only if it was transition-activated. The

hardware-generated LCALL pushes the contents of the Program

Counter on to the stack (but it does not save the PSW) and reloads

the PC with an address that depends on the source of the interrupt

being vectored to, as shown in Table 8.

Execution proceeds from that location until the RETI instruction is

encountered. The RETI instruction informs the processor that this

interrupt routine is no longer in progress, then pops the top two

bytes from the stack and reloads the Program Counter. Execution of

the interrupted program continues from where it left off.

Note that a simple RET instruction would also have returned

execution to the interrupted program, but it would have left the

interrupt control system thinking an interrupt was still in progress,

making future interrupts impossible.

External Interrupts

The external sources can be programmed to be level-activated or

transition-activated by setting or clearing bit IT1 or IT0 in Register

TCON. If ITx = 0, external interrupt x is triggered by a detected low

at the INTx pin. If ITx = 1, external interrupt x is edge triggered. In

this mode if successive samples of the INTx pin show a high in one

cycle and a low in the next cycle, interrupt request flag IEx in TCON

is set. Flag bit IEx then requests the interrupt.

Since the external interrupt pins are sampled once each machine

cycle, an input high or low should hold for at least 12 oscillator

periods to ensure sampling. If the external interrupt is

transition-activated, the external source has to hold the request pin

high for at least one cycle, and then hold it low for at least one cycle.

This is done to ensure that the transition is seen so that interrupt

request flag IEx will be set. IEx will be automatically cleared by the

CPU when the service routine is called.

If the external interrupt is level-activated, the external source has to

hold the request active until the requested interrupt is actually

generated. Then it has to deactivate the request before the interrupt

service routine is completed, or else another interrupt will be

generated.

Response Time

The INT0 and INT1 levels are inverted and latched into IE0 and IE1

at S5P2 of every machine cycle. The values are not actually polled

by the circuitry until the next machine cycle. If a request is active

and conditions are right for it to be acknowledged, a hardware

subroutine call to the requested service routine will be the next

instruction to be executed. The call itself takes two cycles. Thus, a

minimum of three complete machine cycles elapse between

activation of an external interrupt request and the beginning of

execution of the first instruction of the service routine. Figure 25

shows interrupt response timings.

A longer response time would result if the request is blocked by one

of the 3 previously listed conditions. If an interrupt of equal or higher

priority level is already in progress, the additional wait time obviously

depends on the nature of the other interrupt’s service routine. If the

instruction in progress is not in its final cycle, the additional wait time

cannot be more the 3 cycles, since the longest instructions (MUL

and DIV) are only 4 cycles long, and if the instruction in progress is

RETI or an access to IE or IP, the additional wait time cannot be

more than 5 cycles (a maximum of one more cycle to complete the

instruction in progress, plus 4 cycles to complete the next instruction

if the instruction is MUL or DIV).

Thus, in a single-interrupt system, the response time is always more

than 3 cycles and less than 9 cycles.

As previously mentioned, the derivatives described in this data

sheet have a four-level interrupt structure. The corresponding

registers are IE, IP and IPH. (See Figures 22, 23, and 24.) The IPH

(Interrupt Priority High) register makes the four-level interrupt

structure possible.

The function of the IPH SFR is simple and when combined with the

IP SFR determines the priority of each interrupt. The priority of each

interrupt is determined as shown in the following table:

PRIORITY BITS

INTERRUPT PRIORITY LEVEL

IPH.x

IP.x

INTERRUPT PRIORITY LEVEL

Level 0 (lowest priority)

Level 1

Level 2

Level 3 (highest priority)

P80C32 数据表(PDF) 35 Page - NXP Semiconductors

P80C32 数据表(HTML) 35 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表下载

链接网址

P80C32 数据表(PDF) 35 Page - NXP Semiconductors

P80C32 数据表(HTML) 35 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

数据表 下载

链接网址

数据表下载