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AD5378ABC 数据表(PDF) 6 Page - Analog Devices

部件名 AD5378ABC
功能描述  32-Channel, 14-Bit, Parallel and Serial Input, Bipolar Voltage Output DAC
PDF  28 Pages
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制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

AD5378ABC 数据表(HTML) 6 Page - Analog Devices

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AD5378
Rev. PrA | Page 6 of 28
TIMING CHARACTERISTICS
SERIAL INTERFACE
VCC = 2.7 V to 5.5 V; VDD = 11.4 V to 16.5 V; VSS = −11.4 V to −16.5 V; VREF(+) = +5 V; VREF(−) = −3.5 V;
AGND = DGND = REFGND = 0 V; VBIAS = 5 V, FIFOEN = 0 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 5.
Parameter1, ,
2 3
Limit at TMIN, TMAX
Unit
Description
t1
20
ns min
SCLK Cycle Time.
t2
8
ns min
SCLK High Time.
t3
8
ns min
SCLK Low Time.
t4
10
ns min
SYNC Falling Edge to SCLK Falling Edge Setup Time.
t54
15
ns min
24th SCLK Falling Edge to SYNC Falling Edge.
t64
25
ns min
Minimum SYNC Low Time.
t7
10
ns min
Minimum SYNC High Time.
t8
5
ns min
Data Setup Time.
t9
4.5
ns min
Data Hold Time.
t104, 5
30
ns max
24th SCLK Falling Edge to BUSY Falling Edge.
t11
330
ns max
BUSY Pulse Width Low (Single-Channel Update). See Table 11.
t124
20
ns min
24th SCLK Falling Edge to LDAC Falling Edge.
t13
20
ns min
LDAC Pulse Width Low.
t14
150
ns typ
BUSY Rising Edge to DAC Output Response Time.
t15
0
ns min
BUSY Rising Edge to LDAC Falling Edge.
t16
100
ns min
LDAC Falling Edge to DAC Output Response Time.
t17
20/30
µs typ/max
DAC Output Settling Time.
t18
10
ns min
CLR Pulse Width Low.
t19
350
ns max
CLR/RESET Pulse Activation Time.
t206, 7
25
ns max
SCLK Rising Edge to SDO Valid.
t217
5
ns min
SCLK Falling Edge to SYNC Rising Edge.
t227
5
ns min
SYNC Rising Edge to SCLK Rising Edge.
t237
20
ns min
SYNC Rising Edge to LDAC Falling Edge.
t245
30
ns min
SYNC Rising Edge to BUSY Falling Edge.
t25
10
ns min
RESET Pulse Width Low.
t26
120
µs max
RESET Time Indicated by BUSY
Low.
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.
3 See
and
.
Figure 4
Figure 5
4 Standalone mode only.
5 This is measured with the load circuit of
.
Figure 2
6 This is measured with the load circuit of
.
Figure 3
7 Daisy-chain mode only.
TO
OUTPUT
PIN
VCC
VOL
CL
50pF
RL
2.2k
Ω
Figure 2. Load Circuit for BUSY Timing Diagram
2
VOH(min) + VOL(max)
200
µA
200
µA
IOL
IOH
CL
50pF
TO
OUTPUT
PIN
Figure 3. Load Circuit for SDO Timing Diagram
(Serial Interface, Daisy-Chain Mode)



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