Preliminary Technical Data

AD5378

Rev. PrA | Page 13 of 28

Table 9. Pin Function Descriptions

Pin

Description

Logic Power Supply. 2.7 V to 5.5 V. These pins should be decoupled with 0.1 µF ceramic capacitors and 10 µF tantalum

capacitors.

Negative Analog Power Supply. −11.4 V to −16.5 V for specified performance. These pins should be decoupled with

0.1 µF ceramic capacitors and 10 µF tantalum capacitors.

Positive Analog Power Supply. +11.4 V to +16.5 V for specified performance. These pins should be decoupled with

0.1 µF ceramic capacitors and 10 µF tantalum capacitors.

AGND(1–4)

Ground for All Analog Circuitry. All AGND pins should be connected to the AGND plane.

DGND(1–4)

Ground for All Digital Circuitry. All DGND pins should be connected to the DGND plane.

Reference Inputs for DACs 0 to 5, 8 to 13, 16 to 21, and 24 to 30. These voltages are referred to AGND.

Reference Inputs for DACs 6, 7, 14, 15, 22, 23, 30, and 31. These reference voltages are referred to AGND.

DAC Bias Voltage Input/Output. This pin provides an access to the on-chip voltage generator voltage. It is provided

for bypassing and overdriving purposes only.

capacitor to AGND.

VOUT0 to VOUT31

DAC Outputs. Buffered analog outputs for each of the 32 DAC channels. Each analog output can drive an output load

of 5 kΩ to ground. Typical output impedance of these amplifiers is 1 Ω.

SER/PAR

Interface Select Input. This pin allows the user to select whether the serial or parallel interface is used. This pin has an

internal 1 MΩ pull-down resistor, meaning that the default state at power-on is parallel mode. If this pin is tied high,

the serial interface is used.

SYNC1

Active Low Input. This is the frame synchronization signal for the serial interface.

SCLK1

Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds

up to 50 MHz.

DIN1

Serial Data Input. Data must be valid on the falling edge of SCLK.

SDO1

Serial Data Output. CMOS output. SDO can be used for daisy-chaining several devices together. Data is clocked out on

SDO on the rising edge of SCLK and is valid on the falling edge of SCLK.

DCEN1

Daisy-Chain Select Input. Level sensitive, active high. When high, this signal is used in conjunction with SER/PAR high

to enable serial interface daisy-chain mode.

CS

Parallel Interface Chip Select Input. Level sensitive, active low. When this pin is low, the device is selected.

WR

Parallel Interface Write Input. Edge sensitive. The rising edge of WR is used in conjunction with CS low and the

address bus inputs to write to the selected AD5378 registers.

DB13 to DB0

Parallel Data Inputs. The AD5378 can accept a straight 14-bit parallel word on DB0 to DB13, where DB13 is the MSB

and DB0 is the LSB.

A0 to A7

Parallel Address Inputs. A7 to A4 are decoded to select one group or multiple groups of registers (input registers, gain

registers (m), or offset registers (c)) for a data transfer. This pin is used in conjunction with the REG1 and REG0 pins to

determine the destination register for the input data. See the Parallel Interface section for details of the address

decoding.

REG0

Parallel Interface Register Select Input. This pin is used together with REG1 to select data registers, gain registers,

offset registers, increment/decrement mode, or the soft reset function. See Table 12.

REG1

Parallel Interface Register Select Input. This pin is used together with REG0 to select data registers, gain registers,

offset registers, increment/decrement mode, or the soft reset function. See Table 12.

CLR

Asynchronous Clear Input. Level sensitive, active low. When CLR is low, the input to each of the DAC output buffer

stages, VOUT0 to VOUT31, is switched to the externally set potential on the relevant REFGND pin. While CLR is low, all

LDAC pulses are ignored. When CLR is taken high again, the DAC outputs remain cleared until LDAC is taken low. The

contents of input registers and DAC Registers 0 to 31 are not affected by taking CLR low.

BUSY

Digital Input/Open-Drain Output. This pin must be pulled high with a pull-up resistor for correct operation. BUSY goes

low during internal calculations of x2. During this time, the user can continue writing new data to additional ×1, c,

and m registers (these are stored in a FIFO), but no further updates to the DAC registers and DAC outputs can take

place. If LDAC is taken low while BUSY is low, this event is stored. Because BUSY is bidirectional, it can be pulled low

externally to delay LDAC action. BUSY also goes low during power-on reset or when the RESET pin is low. During a

RESET operation, the parallel interface is disabled and any events on LDAC are ignored.

LDAC

Load DAC Logic Input. Active low. If LDAC is taken low while BUSY is inactive (high), the contents of the input

registers are transferred to the DAC registers, and the DAC outputs are updated. If LDAC is taken low while BUSY is

active and internal calculations are taking place, the LDAC event is stored and the DAC registers are updated when

BUSY goes inactive. However, any events on LDAC during power-on reset or RESET are ignored.