AD5378ABC datasheet(20/28 Pages) AD

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AD5378

Rev. PrA | Page 20 of 28

CALIBRATION

The user can perform a system calibration by overwriting the

default values in the m and c registers for any individual DAC

channel as follows:

Calculate the nominal offset and gain coefficients for the

new output range (see the revious example).

Calculate the new m and c values for each channel based

on the specified offset and gain errors.

Calibration Example

Nominal Offset Coefficient = 0

Nominal Gain Coefficient = 10/10.5 × 8191 = 0.95238 × 8191

= 7801

Example 1: Channel 0, Gain Error = 3%,

Offset Error = 100 mV

Gain Error (3%) Calibration: 7801 × 1.03 = 8035

=> Load Code 1 1111 0110 0011 to m Register 0

Offset Error (100 mV) Calibration:

LSB Size = 10.5 / 16384 = 641 µV;

Offset Coefficient for 100 mV Offset = 100 / 0.64 = 156 LSBs

=> Load 10 0000 1001 1100 to c Register 0

Example 2: Channel 1, Gain Error = −3%,

Offset Error = −100 mV

Gain Error (−3%) Calibration: 7801 × 0.97 = 7567

=> Load Code 1 1110 1000 1111 to m Register 1

Offset Error (−100 mV) Calibration:

LSB Size = 10.5 / 16384 = 641 µV;

Offset Coefficient for −100 mV Offset = −100 / 0.64 =

−156 LSBs

=> Load 01 1111 0110 0100 to c Register 1

CLEAR FUNCTION

The clear function on the AD5378 can be implemented in

hardware or software.

Hardware Clear

Bringing the CLR pin low switches the outputs, VOUT0 to

VOUT31, to the externally set potential on the REFGND pin.

This is achieved by switching in REFGND and reconfiguring

the output amplifier stages into unity gain buffer mode, thus

ensuring that VOUT is equal to REFGND. The contents of the

input registers and DAC registers are not affected by taking

CLR low. When CLR is brought high, the DAC outputs remain

cleared until LDAC is taken low. While CLR is low, the value of

LDAC is ignored.

Software Clear

Loading a clear code to the x1 registers also enables the user to

set VOUT0 to VOUT31 to the REFGND level. The default clear

code corresponds to m at full scale and c at midscale (x2 = x1).

Default Clear Code

= 214 × (−Output Offset)/(Output Range)

= 214 × 2.5 × (AGND − VREF(−))/(3.5 × (VREF(+)− AGND))

The more general expression for the clear code is as follows:

Clear Code = (214)/(m + 1) × (Default Clear Code − c)

BUSY AND LDAC FUNCTIONS

The value of x2 is calculated each time the user writes new data

to the corresponding x1, c, or m registers. During the calcula-

tion of x2, the BUSY output goes low. While BUSY is low, the

user can continue writing new data to the x1, m, or c registers,

but no DAC output updates can take place. The DAC outputs

are updated by taking the LDAC input low. If LDAC goes low

while BUSY is active, the LDAC event is stored and the DAC

outputs update immediately after BUSY goes high. A user can

also hold the LDAC input permanently low. In this case, the

DAC outputs update immediately after BUSY goes high.

Table 11. BUSY Pulse Width

BUSY Pulse Width (ns max)

Action

FIFO

Enabled

FIFO

Disabled

Loading x1, c, or m to 1 channel

530

330

Loading x1, c, or m to 2 channels

700

500

Loading x1, c, or m to 3 channels

900

700

Loading x1, c, or m to 4 channels

1050

850

Loading x1, c, or m to all 32

channels

5500

5300

The value of x2 for a single channel or group of channels is

recalculated each time there is a write to any x1 register(s), c

goes low. The duration of this BUSY pulse depends on the

number of channels being updated. For example, if x1, c, or m

data is written to one DAC channel, BUSY goes low for 550 ns

(max). However, if data is written to two DAC channels, BUSY

goes low for 700 ns (max). There are approximately 200 ns of

overhead due to FIFO access. See Table 11.

The AD5378 contains an additional feature whereby a DAC

the last time LDAC was brought low. Normally, when LDAC is

brought low, the DAC registers are filled with the contents of

the x2 registers. However, the AD5378 updates the DAC register

only if the x2 data changes, thereby removing unnecessary

digital crosstalk.

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