R2000 datasheet(16/75 Pages) ETC

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Indy® R2000 Electrical, Mechanical, & Thermal Specification

signal with suppressed negative frequencies. The signal is then offset in frequency to center the SSB-ASK spectrum

in the channel. Sigma-delta DACs convert the digital I and Q signals into the analog domain.

In DSB-ASK transmission, the Indy R2000 reader chip performs the baseband encoding and pulse shaping in the

same manner as for SSB-ASK, but pre-distorts the shaped signal to compensate for non-linearity in the amplitude

modulation transfer function. Sigma-delta DACs convert the pre-distorted, amplitude-modulated control signal into

the analog domain using lookup tables.

The receiver is in principle a homodyne to ensure that as much as possible of the transmitter leakage falls on DC.

You can either drive the receiver down-conversion mixer using the internal local oscillator (LO) signal, or by an

external local oscillator signal, typically tapped off from the output of the external power amplifier. The receiver uses

a single on-chip, low noise amplifier (LNA). If the system must accommodate a >+10 dBm jammer, an external

attenuator is required to reduce the incident power to +10 dBm.

After down conversion, resettable AC-coupling capacitors remove the majority of the DC signal. The analog

intermediate frequency (IF) filter provides coarse channel selectivity. It has programmable bandwidth to

accommodate the large range of required data rates. The coarsely filtered I and Q signals are analog-to-digital

converted. Automatic intermediate frequency gain stepping in the filter reduces the required dynamic range of the

analog-to-digital converter (ADC). Sharp and well-controlled digital filtering supplements the coarse analog filtering.

Digital logic also performs the demodulation.

The reader chip logic derives the clocks for the digital blocks from a 24 MHz reference frequency signal originating

from an external temperature-compensated crystal oscillator (TCXO). The sigma-delta DACs run directly off the

24 MHz signal. The sigma-delta ADCs run off a 48 MHz clock generated by an integrated frequency doubler.

The Indy R2000 includes a fully integrated voltage-controlled oscillator (VCO). The loop filter is external so that the

synthesizer meets the stringent phase noise requirements and allows flexibility. The reader chip logic derives the

time reference required by the phase locked loop and the digital blocks from the 24-MHz reference frequency.

The Indy R2000 reader chip supports two interfaces

—one low speed parallel interface with a data rate of up to

20 Mbps and one serial interface with data rates of 150 Mbps to (downstream), and up to 450 Mbps from (upstream)

the Indy R2000 reader chip. The interfaces are multiplexed on the same pins, and the interface is determined during

power-up. Both interfaces operate at 3.3 V. The Indy R2000 executes one low level instruction at a time from those

written into a first in, first out buffer. All information is transferred via the register bank, and state machines control

the reader chip.

5.1

Analog Receiver Data Path

5.1.1 Receiver Front-end Circuitry

The RF low noise amplifier and mixer can handle a +10 dBm self-jammer when the self-jammer cancellation is

active. For the reader chip sub-system to accommodate a >+10 dBm self-jammer, you must add an external pad.

The combined pad and balun losses should amount to the difference between the self-jammer power and 10 dBm.

The local oscillator input must be +10 dBm in order for the self-jammer cancellation circuitry to have the ability to

cancel the received +10 dBm self-jammer.

Figure 4-1: Receiver Front-end External Input Interface

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