AD5372BCPZ datasheet(6/25 Pages) AD

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AD5372/AD5373

Preliminary Technical Data

Rev. P

rF| Page 6 of 25

TIMING CHARACTERISTICS

DVCC = 2.3 V to 5.5 V; VDD = 8 V to 16.5 V; VSS = −4.5 V to −16.5 V; VREF = 3 V; AGND = DGND = SIGGND = 0 V;

RL = Open Circuit; Gain (m), Offset(c) and DAC Offset registers at default value; all specifications TMIN to TMAX, unless otherwise noted.

SPI INTERFACE (Figure 4 and Figure 5)

Parameter1, 2, 3

Limit at TMIN, TMAX

Unit

Description

ns min

SCLK Cycle Time.

ns min

SCLK High Time.

ns min

SCLK Low Time.

ns min

SYNC Falling Edge to SCLK Falling Edge Setup Time.

ns min

Minimum SYNC High Time.

ns min

24th SCLK Falling Edge to SYNC Rising Edge.

ns min

Data Setup Time.

ns min

Data Hold Time.

t93

ns max

SYNC Rising Edge to BUSY Falling Edge.

t10

1.25

µs max

BUSY Pulse Width Low (Single-Channel Update.) See Table 7.

t11

500

ns max

Single-Channel Update Cycle Time

t12

ns min

24th SCLK Falling Edge to LDAC Falling Edge.

t13

ns min

LDAC Pulse Width Low.

t14

µs max

BUSY Rising Edge to DAC Output Response Time.

t15

ns min

BUSY Rising Edge to LDAC Falling Edge.

t16

µs max

LDAC Falling Edge to DAC Output Response Time.

t17

20/30

µs typ/max

DAC Output Settling Time.

t18

125

ns max

CLR/RESET Pulse Activation Time.

t19

330

ns min

RESET Pulse Width Low.

t20

400

µs max

RESET Time Indicated by BUSY

Low.

t21

270

ns min

Minimum SYNC High Time in Readback Mode.

t225

ns max

SCLK Rising Edge to SDO Valid.

1 Guaranteed by design and characterization, not production tested.

2 All input signals are specified with tr = tf = 2 ns (10% to 90% of VCC) and timed from a voltage level of 1.2 V.

3 See Figure 4 and Figure 5.

4 This is measured with the load circuit of Figure 2.

5 This is measured with the load circuit of Figure 3.

OUTPUT

VCC

2.2k

Ω

50pF

VOL

200µA

50pF

IOL

VOH(min)-VOL (max)

OUTPUT

Figure 2. Load Circuit for BUSY Timing Diagram

Figure 3. Load Circuit for SDO Timing Diagram

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