Preliminary Technical Data

AD5372/AD5373

Rev. P

rF | Page 9 of 25

NC

NC

NC

VDD

VOUT5

VOUT4

SIGGND0

VOUT3

VOUT2

VOUT1

VOUT0

VREF0

VOUT23

VOUT22

VOUT21

VOUT20

39

38

37

41

40

VSS

VDD

SIGGND2

VOUT19

36

35

34

33

42

43

44

45

46

47

48

17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

64 63 62 61 60 59 58

PIN 1

IDENTIFIER

AD5372

AD5373

TOP VIEW

(Not to Scale)

RESET

BUSY

VOUT27

SIGGND3

VOUT28

VOUT29

VOUT30

VOUT31

NC

NC

NC

NC

13

14

15

16

25 26 27

31

30

29

28

32

57 56 55 54 53 52 51 50 49

100605

Figure 6.64-Lead LQFP

Pin Configuration

1

2

3

4

5

6

7

8

9

10

11

12

13

14

42

41

40

39

38

37

36

35

34

33

32

31

30

29

LDAC

CLR

RESET

BUSY

VOUT27

SIGGND3

VOUT28

VOUT29

VOUT30

VOUT31

NC

VDD

VSS

VREF1

NC = NO CONNECT

PIN 1

INDICATOR

AD5372/

AD5373

TOP VIEW

(Not to scale)

VOUT5

VOUT4

SIGGND0

VOUT3

VOUT2

VOUT1

VOUT0

VREF0

VOUT23

VOUT22

VOUT21

VOUT20

VSS

VDD

5372-0060

Figure 7. 56-Lead LFCSP

Pin Configuration

Table 5. Pin Function Descriptions

Pin

Function

Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 µF ceramic capacitors and 10 µF

capacitors.

Negative Analog Power Supply; −11.4 V to −16.5 V for specified performance. These pins should be decoupled with

0.1 µF ceramic capacitors and 10 µF capacitors.

Positive Analog Power Supply; +11.4 V to +16.5 V for specified performance. These pins should be decoupled with

0.1 µF ceramic capacitors and 10 µF capacitors.

AGND

Ground for All Analog Circuitry. All AGND pins should be connected to the AGND plane.

DGND

Ground for All Digital Circuitry. All DGND pins should be connected to the DGND plane.

Reference Input for DACs 0 to 7. This reference voltage is referred to AGND.

Reference Input for DACs 8 to 31. This reference voltage is referred to AGND.

VOUT0 to VOUT31

DAC Outputs. Buffered analog outputs for each of the 40 DAC channels. Each analog output is capable of driving an

output load of 10 kΩ to ground. Typical output impedance of these amplifiers is 1 Ω.

Active Low Input. This is the frame synchronization signal for the serial interface.

Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This pin operates at clock speeds

up to 50 MHz.

Serial Data Input. Data must be valid on the falling edge of SCLK.

Serial Data Output. CMOS output. SDO can be used for readback. Data is clocked out on SDO on the rising edge of

SCLK and is valid on the falling edge of SCLK.

CLR

Asynchronous Clear Input (level sensitive, active low). See the Clear Function section for more information

LDAC

Load DAC Logic Input (Active Low).See the BUSY AND LDAC FUNCTIONS section for more information.

RESET

Asynchronous Digital Reset Input.