AD5372BCPZ datasheet(18/25 Pages) AD

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AD5372/AD5373

Preliminary Technical Data

Rev. P

rF | Page 18 of 25

SERIAL INTERFACE

The AD5372/AD5373 contains a high-speed SPI serial interface

operating at clock frequencies up to 50 MHz (20MHz for read

operations). To minimize both the power consumption of the

device and on-chip digital noise, the interface powers up fully

only when the device is being written to, that is, on the falling

edge of SYNC. The serial interface is 2.5 V LVTTL compatible

when operating from a 2.7 V to 3.6 V DVCC supply. It is

controlled by four pins, as follows.

SYNC

Frame synchronization input.

SDI

Serial data input pin.

SCLK

Clocks data in and out of the device.

SDO

Serial data output pin for data readback.

SPI WRITE MODE

The AD5372AD5373 allows writing of data via the serial

interface to every register directly accessible to the serial

interface, which is all registers except the X2A and X2B

registers and the DAC registers. The X2A and X2B registers are

updated when writing to the X1A, X1B, M and C registers, and

the DAC registers are updated by LDAC. The serial word (see

Table 8 or Table 9) is 24 bits long. 16 or 14 of these bits are data

bits, six bits are address bits, and two bits are mode bits that

determine what is done with the data. Two bits are reserved on

the AD5373.

The serial interface works with both a continuous and a burst

(gated) serial clock. Serial data applied to SDI is clocked into

the AD5372AD5373 by clock pulses applied to SCLK. The first

falling edge of SYNC starts the write cycle. At least 24 falling

clock edges must be applied to SCLK to clock in 24 bits of data,

before SYNC is taken high again. If SYNC is taken high before

the 24th falling clock edge, the write operation will be aborted.

If a continuous clock is used, SYNC must be taken high before

the 25th falling clock edge. This inhibits the clock within the

AD5372/AD5373. If more than 24 falling clock edges are

applied before SYNC is taken high again, the input data will be

corrupted. If an externally gated clock of exactly 24 pulses is

used, SYNC may be taken high any time after the 24th falling

clock edge.

The input register addressed is updated on the rising edge of

SYNC. In order for another serial transfer to take place, SYNC

must be taken low again

Table 8. AD5372 Serial Word Bit Assignation

I23

I22

I21

I20

I19

I18

I17

I16

I15

I14

I13

I12

I11

I10

D15

D14

D13

D12

D11

D10

Table 9. AD5373 Serial Word Bit Assignation

I23

I22

I21

I20

I19

I18

I17

I16

I15

I14

I13

I12

I11

I10

I1*

I0*

D13

D12

D11

D10

*Reserved bits. Set to 0 when writing. Bits are read back as 0

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