AD5372BCPZ datasheet(22/25 Pages) AD

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AD5372/AD5373

Preliminary Technical Data

Rev. P

rF | Page 22 of 25

Table 17. DACs Select by A/B Select Registers

Bits

A/B Select

VOUT7

VOUT6

VOUT5

VOUT4

VOUT3

VOUT2

VOUT1

VOUT0

VOUT15

VOUT14

VOUT13

VOUT12

VOUT11

VOUT10

VOUT9

VOUT8

VOU23

VOUT22

VOUT21

VOUT20

VOUT19

VOUT18

VOUT17

VOUT16

VOUT31

VOUT30

VOUT29

VOUT28

VOUT27

VOUT26

VOUT25

VOUT24

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful considera-

tion of the power supply and ground return layout helps to

ensure the rated performance. The printed circuit board on

which the AD5372/AD5373 is mounted should be designed so

that the analog and digital sections are separated and confined

to certain areas of the board. If the AD5372/AD5373 is in a

system where multiple devices require an AGND-to-DGND

connection, the connection should be made at one point only.

The star ground point should be established as close as possible

to the device. For supplies with multiple pins (VSS, VDD, VCC), it

is recommended to tie these pins together and to decouple each

supply once.

The AD5372/AD5373 should have ample supply decoupling of

10 µF in parallel with 0.1 µF on each supply located as close to

the package as possible, ideally right up against the device. The

10 µF capacitors are the tantalum bead type. The 0.1 µF capaci-

tor should have low effective series resistance (ESR) and

effective series inductance (ESI), such as the common ceramic

types that provide a low impedance path to ground at high

frequencies, to handle transient currents due to internal logic

switching.

Digital lines running under the device should be avoided,

because these couple noise onto the device. The analog ground

plane should be allowed to run under the AD5372/AD5373 to

avoid noise coupling. The power supply lines of the

AD5372/AD5373 should use as large a trace as possible to

provide low impedance paths and reduce the effects of glitches

on the power supply line. Fast switching digital signals should

be shielded with digital ground to avoid radiating noise to other

parts of the board, and should never be run near the reference

inputs. It is essential to mini mize noise on all VREF lines.

Avoid crossover of digital and analog signals. Traces on

opposite sides of the board should run at right angles to each

other. This reduces the effects of feedthrough through the

board. A microstrip technique is by far the best, but not always

possible with a double-sided board. In this technique, the

component side of the board is dedicated to ground plane,

while signal traces are placed on the solder side.

As is the case for all thin packages, care must be taken to avoid

flexing the package and to avoid a point load on the surface of

this package during the assembly process.

POWER SUPPLY SEQUENCING

When the supplies are connected to the AD5372/AD5373 it is

important that the AGND and DGND pins are connected to the

relevant ground plane before the positive or negative supplies

are applied. In most applications this is not an issue as the

ground pins for the power supplies will be connected to the

ground pins of the AD5372/AD5373 via ground planes. Where

the AD5372/AD5373 is to be used in a hot-swap card care

should be taken to ensure that the ground pins are connected to

the supply grounds before the positive or negative supplies are

connected. This is required to prevent currents flowing in

directions other than towards an analog or digital ground.

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