AD5372BCPZ datasheet(16/25 Pages) AD

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AD5372/AD5373

Preliminary Technical Data

Rev. P

rF | Page 16 of 25

RESET FUNCTION

When the RESET pin is taken low, the DAC buffers are

disconnected and the DAC outputs VOUT0 to VOUT31 are

tied to their associated SIGGND signals via a 10 kΩ resistor. On

the rising edge of RESET the AD5372/AD5373 state machine

initiates a reset sequence to reset the X, M and C registers to

their default values. This sequence typically takes 300µs and the

user should not write to the part during this time. When the

reset sequence is complete, and provided that CLR is high, the

DAC output will be at a potential specified by the default

DAC outputs will remain at SIGGND until the X, M or C

registers are updated and LDAC is taken low.

CLEAR FUNCTION

CLR is an active low input which should be high for normal

operation. The CLR pin has in internal 500kΩ pull-down

resistor. When CLR is low, the input to each of the DAC output

buffer stages, VOUT0 to VOUT31, is switched to the externally

set potential on the relevant SIGGND pin. While CLR is low, all

LDAC pulses are ignored. When CLR is taken high again, the

DAC outputs remain cleared until LDAC is taken low. The

contents of input registers and DAC registers 0 to 31 are not

affected by taking CLR low. To prevent glitches appearing on

the outputs CLR should be brought low whenever the output

span is adjusted by writing to the offset DAC.

BUSY AND LDAC FUNCTIONS

The value of an X2 (A or B) register is calculated each time the

user writes new data to the corresponding X1, C, or M registers.

During the calculation of X2, the BUSY output goes low. While

BUSY is low, the user can continue writing new data to the X1,

M, or C registers (see the Register Update Rates section for

more details), but no DAC output updates can take place.

The BUSY pin is bidirectional and has a 50 kΩ internal pullup

resistor. Where multiple AD5372 or AD5373 devices may be

used in one system the BUSY pins can be tied together. This is

useful where it is required that no DAC in any device is updated

until all other DACs are ready. When each device has finished

updating the X2 (A or B) registers it will release the BUSY pin.

If another device hasn’t finished updating its X2 registers it will

hold BUSY low, thus delaying the effect of LDAC going low.

The DAC outputs are updated by taking the LDAC input low. If

LDAC goes low while BUSY is active, the LDAC event is stored

and the DAC outputs update immediately after BUSY goes

high. A user can also hold the LDAC input permanently low. In

this case, the DAC outputs update immediately after BUSY

goes high. BUSY also goes low, for approximately 500ns,

whenever the A/B Select Registers are written to.

As described later, the ADAD5372/AD5373 has flexible

addressing that allows writing of data to a single channel, all

channels in a group, the same channel in groups 0 to 3 or

groups 1 to 4, or all channels in the device. This means that 1, 4,

8 or 32 DAC register values may need to be calculated and

updated. As there is only one multiplier shared between 32

channels, this task must be done sequentially, so the length of

the BUSY pulse will vary according to the number of channels

being updated.

Table 7. BUSY Pulse Widths

Action

BUSY Pulse Width

(µs max)

Loading Input, C, or M to 1 channel

1.25

Loading Input, C, or M to 4 channels

2.75

Loading Input, C, or M to 8 channels

4.75

Loading Input, C, or M to 32 channels

16.75

BUSY Pulse Width = ((Number of Channels +1) × 500ns) +250ns

The AD5372/AD5373 contains an extra feature whereby a DAC

written to since the last time LDAC was brought low. Normally,

when LDAC is brought low, the DAC registers are filled with

the contents of the X2A or X2B registers, depending on the

setting of the A/B Select Registers. However the

AD5372/AD5373 updates the DAC register only if the X2 data

has changed, thereby removing unnecessary digital crosstalk.

POWER-DOWN MODE

The AD5372/AD5373 can be powered down by setting Bit 0 in

the control register. This will turn off the DACs thus reducing

the current consumption. The DAC outputs will be connected

to their respective SIGGND potentials. The power-down mode

doesn’t change the contents of the registers and the DACs will

return to their previous voltage when the power-down bit is

cleared.

THERMAL MONITOR FUNCTION

The AD5372/AD5373 can be programmed to power down the

DACs if the temperature on the die exceeds 130°C. Setting Bit 1

in the control register (see Table 15) will enable this function. If

the die temperature exceeds 130°C the AD5372/AD5373 will

enter a temperature power-down mode, which is equivalent to

setting the power-down bit in the control register. To indicate

that the AD5372/AD5373 has entered temperature power-down

mode Bit 4 of the control register is set. The AD5372/AD5373

will remain in temperature shutdown mode, even if the die

temperature falls, until Bit 1 in the control register is cleared.

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