Preliminary Technical Data

AD5372/AD5373

Rev. P

rF | Page 13 of 25

A/ B REIGSTERS AND GAIN/OFFSET ADJUSTMENT

Each DAC channel has seven data registers. The actual DAC

data word can be written to either the X1A or X1B input

register, depending on the setting of the A/B bit in the Control

Register. If the A/B bit is 0, data will be written to the X1A

register. If the A/B bit is 1, data will be written to the X1B

register. Note that this single bit is a global control and affects

every DAC channel in the device. It is not possible to set up the

device on a per-channel basis so that some writes are to X1A

registers and some writes are to X1B registers.

DAC

DAC

REGISTER

MUX

X2B

REGISTER

X2A

REGISTER

MUX

M

REGISTER

C

REGISTER

X1B

REGISTER

X1A

REGISTER

Figure 8. Data Registers Associated With Each DAC Channel

Each DAC channel also has a gain (M) and offset (C) register,

which allow trimming out of the gain and offset errors of the

entire signal chain. Data from the X1A register is operated on

by a digital multiplier and adder controlled by the contents of

the M and C registers. The calibrated DAC data is then stored in

the X2A register. Similarly, data from the X1B register is

operated on by the multiplier and adder and stored in the X2B

register.

Although a multiplier and adder symbol are shown for each

channel, there is only one multiplier and one adder in the

device, which are shared between all channels. This has

implications for the update speed when several channels are

updated at once, as described later.

Each time data is written to the X1A register, or to the M or C

register with the A/B control bit set to 0, the X2A data is

recalculated and the X2A register is automatically updated.

Similarly, X2B is updated each time data is written to X1B, or to

M or C with A/B set to 1. The X2A and X2B registers are not

readable, nor directly writable by the user.

Data output from the X2A and X2B registers is routed to the

final DAC register by a multiplexer. Whether each individual

DAC takes its data from the X2A or X2B register is controlled

by an 8-bit A/B Select Register associated with each group of 8

DACs. If a bit in this register is 0, the DAC takes its data from

the X2A register; if 1 the DAC takes its data from the X2B

register (bit 0 controls DAC 0 through bit 7 controls DAC 7).

Note that, since there are 32 bits in 4 registers, it is possible to

set up, on a per-channel basis, whether each DAC takes its data

from the X2A or X2B register. A global command is also

provided that sets all bits in the A/B Select Registers to 0 or to 1.

LOAD DAC

All DACs in the AD5372/AD5373 can be updated

simultaneously by taking LDAC low, when each DAC register

will be updated from either its X2A or X2B register, depending

on the setting of the A/B select registers. The DAC register is

not readable, nor directly writable by the user.

OFFSET DACS

In addition to the gain and offset trim for each DAC, there are

two 14-bit Offset DACs, one for Group 0, and one for Group 1

to Group 3. These allow the output range of all DACs connected

to them to be offset within a defined range. Thus, subject to the

limitations of headroom, it is possible to set the output range of

Group 0 or Group 1 to Group3 to be unipolar positive, unipolar

negative, or bipolar, either symmetrical or asymmetrical about

zero volts. The DACs in the AD5372/AD5373 are factory

trimmed with the Offset DACs set at their default values. This

gives the best offset and gain performance for the default

output range and span.

When the output range is adjusted by changing the value of the

Offset DAC an extra offset is introduced due to the gain error

of the Offset DAC. The amount of offset is dependent on the

magnitude of the reference and how much the Offset DAC

moves from its default value. This offset is quoted on the

specification page. The worst case offset occurs when the Offset

DAC is at positive or negative full-scale. This value can be

added to the offset present in the main DAC of a channel to

give an indication of the overall offset for that channel. In most

cases the offset can be removed by programming the channels

C register with an appropriate value. The extra offset cause by

the Offset DACs only needs to be taken into account when the

Offset DAC is changed from its default value. Figure 9 shows

the allowable code range which may be loaded to the Offset

DAC and this is dependant on the reference value used. Thus,

for a 5V reference, the Offset DAC should not be programmed

with a value greater than 8192 (0x2000).

0

4096

8192

12288

16383

OFFSET DAC CODE

0

1

2

3

4

RESERVED

5

Figure 9. Offset DAC Code Range