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TMD3721 数据表(PDF) 63 Page - ams AG |
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TMD3721 数据表(HTML) 63 Page - ams AG |
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63 / 89 page  Page 62 Datasheet, Public Document Feedback [v3-00] 2023-May-26 TMD3721 − Register O ver view AWTIME Register (Address 0xE7) Figure 87: AWTIME Register The AWTIME is implemented using a down counter and starts counting from very beginning of every ALS integration cycle. If enabled, AWTIME needs to be programmed greater than ATIME, otherwise ATIME takes precedence over AWTIME. AWTIME = Wait Cycles x2.779ms. If AWLONG is enabled, then AWTIME =Wait Cycles x2.779ms x12. Addr: 0xE7 AWTIME Bit Bit Name Default Access Bit Description 7:0 AWTIME 0x00 RW Value that specifies the wait time in 2.779ms increments Value Wait Cycles Wait Time 0x00 1 2.779ms (33.346ms) 0x01 2 5.558ms (66.692ms) 0x02 3 8.336ms (100.038ms) …… … 0x1F 32 88.923ms (1.067s) …… … 0xFF 256 711.381ms (8.537s) |
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