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TMD3721 数据表(PDF) 46 Page - ams AG |
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TMD3721 数据表(HTML) 46 Page - ams AG |
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46 / 89 page  Datasheet, Public Page 45 [v3-00] 2023-May-26 Document Feedback TMD3721 − Register Overview RESET Register (Address 0xA8) Figure 59: RESET Register Addr: 0xA8 RESET Bit Bit Name Default Access Bit Description 7:4 Reserved 0000 RW Reserved. Must be set to default value. 3 INV_XRES 0 RW Inverts XRES pin input. 2ENAB_XRES 0 RW Enable XRES as a hardware reset pin. By default, level high triggers a device reset. 1 HARD_RESET 0 RW Perform a POR cycle when this bit is set. 0SOFT_RESET 0 RW Software Reset. Writing a ‘1’ triggers a reset of all I²C registers to default states, including SOFT_RESET bit itself. Due to the reset of PON, a running ALS and Proximity is aborted and the oscillator is turned off. SOFT_RESET will not set POWER_ON_RESET status bit. |
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