TMD3721 datasheet(13/89 Pages) AMSCO

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Datasheet, Public

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[v3-00] 2023-May-26

TMD3721 − Detailed Description

Power Up

Upon power-up, device initialization occurs. During

initialization, the device cannot accept I²C transactions and will

deterministically send NAK for any I²C requests. All

communication with the device must be delayed, and all

outputs from the device (i.e. interrupts) must be ignored until

initialization completes. After initialization, the device enters

the SLEEP state in which the internal oscillator and other

circuitry are not active, resulting in ultra-low power

consumption. If an I²C transaction occurs during the SLEEP

state, the I²C core wakes up temporarily to service the

communication. When the Power ON bit, PON, is enabled, the

device enters the IDLE state in which the internal oscillator and

attendant circuitry are active, but power consumption remains

low. After PON is set, there is a 100μs wait time required before

enabling PEN, AEN. This allows the device time to settle the

internal node voltages and currents before starting the

Proximity and ALS measurements. When a function is enabled

(PEN=1 and/or AEN =1), the device exits the IDLE state. When

both functions are disabled (PEN=0 & AEN=0), the device

returns to the IDLE state.

As depicted in Figure 13, the proximity and CRGB color sensing

functions can operate in parallel when both are enabled (PEN

= AEN = 1). Each function is individually configured (e.g. gain,

ADC integration time, wait time, persistence, thresholds, etc.).

When a proximity calibration is requested, it will take

precedence over the proximity measurement function. If Sleep

After Interrupt is enabled (SAI = 1 in register 0xAB, available

only in sequential mode), the state machine will enter SLEEP

when an interrupt occurs. Entering SLEEP will not change any

of the register settings (e.g. PON will still be high, but the normal

operational state is over-ridden by SLEEP state). SLEEP state is

terminated when the interrupt status register is cleared (the

status bit is in register 0xA0-0xA2).

Figure 13:

Simplified State Diagram

Detailed Description

SLEEP

IDLE

PON

ALS

CRGB

PROXIMITY

PARALLEL

FUNCTIONS

AEN

PEN

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